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Table 9-21.
Steps For Dynamically Loading the Mini Instruction Cache
Action
Step #
Debugger
1
Poll DBGTX
2
3
Detect handler
34
write to TX
Load LDIC Instr
5
and download
code
clock a minimum
of 20 TCKs before
6
changing the
JTAG IR.
7
Write RX
8
Note: The debug handler polling loop must reside in the instruction cache and execute out of the cache
while doing the synchronization. The processor should not be doing any code fetches to external
memory while code is being downloaded.
Developer's Manual
Debug Handler
Debugger must poll DBGTX for an indication from the debug handler that it is
safe to begin the download.
Refer to
DBGTX through JTAG.
When the debug handler gets to a safe section of code, it writes TX, allowing
Write TX,
the debugger to proceed with the download.
The handler then begins polling the RX Ready for an indication the debugger
Poll RX Read Flag
has completed the download
When the debugger sees a valid value in TX, it can proceed with the
download into the instruction cache.
Debugger loads the LDIC instruction into JTAG IR and downloads code into
the instruction cache.
For each cache line downloaded, the debugger must invalidate the target line
before downloading to that line. Failure to invalidate a line prior to writing it
may cause unpredictable operation by the processor.
Refer to
and download functions.
The LDIC JTAG instruction must remain in the JTAG instruction register for at
least 20 TCKs following the update_dr for the last cache line, to ensure that
line is correctly loaded into the mini instruction cache. Changing the JTAG IR
within 20 cycles my result in unpredictable behavior.
The completes the handshaking allowing the handler to exit its polling loop.
The value written to RX by the debugger is implementation specific.
The handler exits is polling loop and depending on the implementation of the
Detect debugger
debug handler, can branch to a fixed address where the code was
write to RX
downloaded or can use the value written to RX be the debugger as the target
address to branch to.
January, 2004
Intel XScale® Core Developer's Manual
Notes
Section 9.11.2, "DBGTX JTAG Register"
Section 9.14.4, "LDIC Cache Functions"
Software Debug
for details on polling
for details on the invalidate
161
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