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Intel XScale® Core Developer's Manual
Introduction
1.2.2.6
Performance Monitoring
Performance monitoring counters have been added to the Intel XScale
to monitor various events in the core. These events allow a software developer to measure cache
efficiency, detect system bottlenecks and reduce the overall latency of programs.
Chapter 8, "Performance Monitoring"
1.2.2.7
Power Management
The Intel XScale
controlling their clocking and managing their power. These features are described in
"CP14 Registers" on page
1.2.2.8
Debug
The Intel XScale
registers, one data-address breakpoint register, one data-address/mask breakpoint register, and a
trace buffer.
Chapter 9, "Software Debug"
1.2.2.9
JTAG
Testability is supported on the Intel XScale
implementation, which is based on IEEE 1149.1 (JTAG) Standard Test Access Port and
Boundary-Scan Architecture. The purpose of the TAP controller is to support test logic internal and
external to the core such as built-in self-test and boundary-scan.
Appendix B
18
®
core incorporates a power and clock management unit that can assist ASSPs in
7-96.
®
core supports software debugging through two instruction address breakpoint
discusses this in more detail.
discusses this in more detail.
January, 2004
discusses this in more detail.
®
core through the Test Access Port (TAP) Controller
®
core that can be configured
Section 7.3,
Developer's Manual
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