Managing The Performance Monitor - Intel XScale Core Developer's Manual

Table of Contents

Advertisement

Intel XScale® Core Developer's Manual
Performance Monitoring
8.3.7

Managing the Performance Monitor

The following are a few notes about controlling the performance monitoring mechanism:
An interrupt request will be generated when a counter's overflow flag is set and its associated
interrupt enable bit is set in INTEN. The interrupt request will remain asserted until software
clears the overflow flag by writing a one to the flag that is set. (Note that the product specific
interrupt unit and the CPSR must have enabled the interrupt in order for software to receive it.)
The interrupt request can also be deasserted by clearing the corresponding interrupt enable bit.
Disabling the facility (PMNC.E) doesn't deassert the interrupt request.
The counters continue to record events even after they overflow.
To change an event for a performance counter, first disable the facility (PMNC.E) and then
modify EVTSEL. Not doing so will cause unpredictable results.
Simultaneously resetting and disabling the counter will cause unpredictable results. To disable
an event for a performance counter and reset the event counter, first disable the facility
(PMNC.E) and then reset the counter.
To increase the monitoring duration, software can extend the count duration beyond 32 bits by
counting the number of overflow interrupts each 32-bit counter generates. This can be done in
the interrupt service routine (ISR) where an increment to some memory location every time
the interrupt occurs will enable longer durations of performance monitoring. This does intrude
upon program execution but is negligible, since the ISR execution time is in the order of tens
of cycles compared to the number of cycles it took to generate an overflow interrupt (2
Power can be saved by selecting event 0xFF for any unused event counter. This only applies
when other event counters are in use. When the performance monitor is not used at all
(PMNC.E = 0x0), hardware ensures minimal power consumption.
112
January, 2004
32
).
Developer's Manual

Advertisement

Table of Contents
loading

Table of Contents