Intel XScale Core Developer's Manual page 12

Intel XScale® Core Developer's Manual
Contents
8-6 Clock Count Register (CCNT) .................................................................................................. 106
8-7 Performance Monitor Count Register (PMN0 - PMN3) ............................................................ 107
8-8 Performance Monitor Control Register ..................................................................................... 108
8-9 Interrupt Enable Register.......................................................................................................... 109
8-10 Overflow Flag Status Register .................................................................................................. 110
8-11 Event Select Register ............................................................................................................... 111
8-12 Performance Monitoring Events ............................................................................................... 113
8-13 Some Common Uses of the PMU ............................................................................................ 114
9-1 Debug Control and Status Register (DCSR) ............................................................................ 123
9-2 Event Priority ............................................................................................................................ 126
9-3 Halt Mode R14_DBG Updating ................................................................................................ 127
9-4 Monitor Mode R14_DBG Updating ........................................................................................... 129
9-5 Instruction Breakpoint Address and Control Register (IBCRx) ................................................. 130
9-6 Data Breakpoint Register (DBRx)............................................................................................. 131
9-7 Data Breakpoint Controls Register (DBCON)........................................................................... 131
9-8 TX RX Control Register (TXRXCTRL)...................................................................................... 134
9-9 Normal RX Handshaking .......................................................................................................... 135
9-10 High-Speed Download Handshaking States ............................................................................ 135
9-11 TX Handshaking ....................................................................................................................... 137
9-12 TXRXCTRL Mnemonic Extensions .......................................................................................... 137
9-13 TX Register............................................................................................................................... 138
9-14 RX Register .............................................................................................................................. 138
9-15 CP 14 Trace Buffer Register Summary .................................................................................... 145
9-16 Checkpoint Register (CHKPTx) ................................................................................................ 146
9-17 TBREG Format ......................................................................................................................... 147
9-18 Message Byte Formats............................................................................................................. 148
9-19 LDIC Cache Functions ............................................................................................................. 156
9-20 Steps For Loading Mini Instruction Cache During Reset.......................................................... 159
9-21 Steps For Dynamically Loading the Mini Instruction Cache ..................................................... 161
10-1 Branch Latency Penalty............................................................................................................ 164
10-2 Latency Example ...................................................................................................................... 166
10-3 Branch Instruction Timings (Those predicted by the BTB) ....................................................... 167
10-4 Branch Instruction Timings (Those not predicted by the BTB) ................................................. 167
10-5 Data Processing Instruction Timings ........................................................................................ 167
10-6 Multiply Instruction Timings ...................................................................................................... 168
10-7 Multiply Implicit Accumulate Instruction Timings ...................................................................... 169
10-8 Implicit Accumulator Access Instruction Timings...................................................................... 169
10-9 Saturated Data Processing Instruction Timings ....................................................................... 170
10-10Status Register Access Instruction Timings............................................................................ 170
10-11Load and Store Instruction Timings ........................................................................................ 171
10-12Load and Store Multiple Instruction Timings........................................................................... 171
10-13Semaphore Instruction Timings .............................................................................................. 171
10-14CP15 Register Access Instruction Timings............................................................................. 172
10-15CP14 Register Access Instruction Timings............................................................................. 172
10-16Exception-Generating Instruction Timings .............................................................................. 172
10-17Count Leading Zeros Instruction Timings ............................................................................... 172
A-1 Pipelines and Pipe stages ........................................................................................................ 177
12 January, 2004 Developer's Manual