Coprocessor Instructions; Miscellaneous Instruction Timing; Cp15 Register Access Instruction Timings; Cp14 Register Access Instruction Timings - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Performance Considerations
10.4.9

Coprocessor Instructions

Table 10-14. CP15 Register Access Instruction Timings
Mnemonic
a
MRC
MCR
a. MRC to R15 is unpredictable
Table 10-15. CP14 Register Access Instruction Timings
Mnemonic
MRC
MRC to R15
MCR
LDC
STC
10.4.10

Miscellaneous Instruction Timing

Table 10-16. Exception-Generating Instruction Timings
Mnemonic
SWI
BKPT
UNDEFINED
Table 10-17. Count Leading Zeros Instruction Timings
Mnemonic
CLZ
172
Minimum Issue Latency
4
2
Minimum Issue Latency
8
9
8
11
8
Minimum latency to first instruction of exception handler
Minimum Issue Latency
1
January, 2004
Minimum Result Latency
4
N/A
Minimum Result Latency
8
9
N/A
N/A
N/A
6
6
6
Minimum Result Latency
1
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