Auxiliary Control Register - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Configuration
The mini-data cache attribute bits, in the Auxiliary Control Register, are used to control the
allocation policy for the mini-data cache and whether it will use write-back caching or
write-through caching.
Note: The configuration of the mini-data cache should be setup before any data access is made that may
be cached in the mini-data cache. Once data is cached, software must ensure that the mini-data
cache has been cleaned and invalidated before the mini-data cache attributes can be changed.
Table 7-7.

Auxiliary Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:6
5:4
3:2
1
0
84
Access
Read-Unpredictable /
Write-as-Zero
Read / Write
Read-Unpredictable /
Write-as-Zero
Read / Write
Read / Write
January, 2004
8
Description
Reserved
Mini Data Cache Attributes (MD)
All configurations of the Mini-data cache are cacheable,
stores are buffered in the write buffer and stores will be
coalesced in the write buffer as long as coalescing is
globally enable (bit 0 of this register).
0b00 = Write back, Read allocate
0b01 = Write back, Read/Write allocate
0b10 = Write through, Read allocate
0b11 = Unpredictable
Reserved
Page Table Memory Attribute (P) This field is defined by
the ASSP. Refer to the Intel XScale
option section of the ASSP architecture specification for
more information.
Write Buffer Coalescing Disable (K)
This bit globally disables the coalescing of all stores in the
write buffer no matter what the value of the Cacheable
and Bufferable bits are in the page table descriptors.
0 = Enabled
1 = Disabled
7 6 5 4 3 2 1 0
MD P K
®
core implementation
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