Saturated Arithmetic Instructions; Status Register Access Instructions; Saturated Data Processing Instruction Timings; Status Register Access Instruction Timings - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Performance Considerations
10.4.5

Saturated Arithmetic Instructions

h
Table 10-9.

Saturated Data Processing Instruction Timings

Mnemonic
QADD
QSUB
QDADD
QDSUB
10.4.6

Status Register Access Instructions

Table 10-10. Status Register Access Instruction Timings
Mnemonic
MRS
MSR
170
Minimum Issue Latency
1
1
1
1
Minimum Issue Latency
1
2 (6 if updating mode bits)
January, 2004
Minimum Result Latency
2
2
2
2
Minimum Result Latency
2
1
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