Basic Optimizations; Conditional Instructions; A.3.1 Conditional Instructions; Optimizing Condition Checks - Intel XScale Core Developer's Manual

A.3

Basic Optimizations

This chapter outlines optimizations specific to ARM architecture. These optimizations have been
modified to suit the core where needed.
A.3.1

Conditional Instructions

The Intel XScale
feature combined with the ability of the core instructions to modify the condition codes makes
possible a wide array of optimizations.
A.3.1.1.

Optimizing Condition Checks

The Intel XScale
generating code for if-else and loop conditions it is often beneficial to make use of this feature to
set condition codes, thereby eliminating the need for a subsequent compare instruction. Consider
the C code segment:
if (a + b)
Code generated for the if condition without using an add instruction to set condition codes is:
;Assume r0 contains the value a, and r1 contains the value b
add
cmp
However, code can be optimized as follows making use of add instruction to set condition codes:
;Assume r0 contains the value a, and r1 contains the value b
adds
The instructions that increment or decrement the loop counter can also be used to modify the
condition codes. This eliminates the need for a subsequent compare instruction. A conditional
branch instruction can then be used to exit or continue with the next loop iteration.
Consider the following C code segment:
for (i = 10; i != 0; i--)
{
do something;
}
The optimized code generated for the above code segment would look like:
L6:
.
.
subs r3, r3, #1
bne
It is also beneficial to rewrite loops whenever possible so as to make the loop exit conditions check
against the value 0. For example, the code generated for the code segment below will need a
compare instruction to check for the loop exit condition.
for (i = 0; i < 10; i++)
{
do something;
}
If the loop were rewritten as follows, the code generated avoids using the compare instruction to
check for the loop exit condition.
for (i = 9; i >= 0; i--)
{
do something;
}
Developer's Manual
®
core architecture provides the ability to execute instructions conditionally. This
®
core instructions can selectively modify the state of the condition codes. When
r0,r0,r1
r0, #0
r0,r0,r1
.L6
January, 2004
Intel XScale® Core Developer's Manual
Optimization Guide
183