Ldc/Stc Format When Accessing Cp14 - Intel XScale Core Developer's Manual

The format of LDC and STC for CP14 is shown in
programming notes in the ARM Architecture Reference Manual. Note that access to CP15 with
LDC and STC will cause an undefined exception and accesses to all other coprocessors is defined
in the Intel XScale
LDC and STC transfer a single 32-bit word between a coprocessor register and memory. These
instructions do not allow the programmer to specify values for opcode_1, opcode_2, or Rm; those
fields implicitly contain zero, which means the performance monitoring registers are not
accessible.
Table 7-2.

LDC/STC Format when Accessing CP14

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
31:28
24:23,21
22
20
19:16
15:12
11:8
7:0
Developer's Manual
®
core implementation option section of the ASSP architecture specification.
1 1 0 P U N W L
Description
cond - ARM* condition codes
P, U, W - specifies 1 of 3 addressing modes
identified by addressing mode 5 in the ARM
Architecture Reference Manual .
N - should be 0 for CP14 coprocessors. Setting
this bit to 1 has will have an undefined effect.
L - Load or Store
0 = STC
1 = LDC
Rn - specifies the base register
CRd - specifies the coprocessor register
cp_num - coprocessor number
8-bit word offset
January, 2004
Intel XScale® Core Developer's Manual
Table 7-2. LDC and STC follow the
Rn CRd cp_num
-
-
-
-
-
The Intel XScale
0b1111 = Undefined Exception
0b1110 = CP14
NOTE: Refer to the Intel XScale
implementation option section of the
ASSP architecture specification to find
out the meaning of the other
encodings.
-
Configuration
8 7 6 5 4 3 2 1
8_bit_word_offset
Notes
®
core defines the following:
®
core
79
0