Intel XScale Core Developer's Manual page 11

Tables
2-1 Multiply with Internal Accumulate Format ................................................................................... 24
2-2 MIA{<cond>} acc0, Rm, Rs ........................................................................................................25
2-3 MIAPH{<cond>} acc0, Rm, Rs ................................................................................................... 25
2-4 MIAxy{<cond>} acc0, Rm, Rs..................................................................................................... 26
2-5 Internal Accumulator Access Format..........................................................................................27
2-6 MAR{<cond>} acc0, RdLo, RdHi ................................................................................................ 28
2-7 MRA{<cond>} RdLo, RdHi, acc0 ................................................................................................ 28
2-9 Second-level Descriptors for Coarse Page Table.......................................................................30
2-10 Second-level Descriptors for Fine Page Table ........................................................................... 30
2-8 First-level Descriptors ................................................................................................................. 30
2-11 Exception Summary....................................................................................................................32
2-12 Event Priority .............................................................................................................................. 32
2-13 Encoding of Fault Status for Prefetch Aborts..............................................................................33
2-14 Encoding of Fault Status for Data Aborts ................................................................................... 34
3-1 Data Cache and Buffer Behavior when X = 0 ............................................................................. 39
3-2 Data Cache and Buffer Behavior when X = 1 ............................................................................. 39
3-3 Memory Operations that Impose a Fence .................................................................................. 40
3-4 Valid MMU & Data/mini-data Cache Combinations .................................................................... 41
7-1 MRC/MCR Format ......................................................................................................................78
7-2 LDC/STC Format when Accessing CP14 ................................................................................... 79
7-3 CP15 Registers...........................................................................................................................80
7-4 ID Register..................................................................................................................................81
7-5 Cache Type Register .................................................................................................................. 82
7-6 ARM* Control Register ...............................................................................................................83
7-7 Auxiliary Control Register ........................................................................................................... 84
7-8 Translation Table Base Register ................................................................................................ 85
7-9 Domain Access Control Register................................................................................................ 85
7-10 Fault Status Register .................................................................................................................. 86
7-11 Fault Address Register ...............................................................................................................86
7-12 Cache Functions......................................................................................................................... 87
7-13 TLB Functions............................................................................................................................. 89
7-14 Cache Lockdown Functions........................................................................................................90
7-15 Data Cache Lock Register.......................................................................................................... 90
7-16 TLB Lockdown Functions ........................................................................................................... 91
7-17 Accessing Process ID................................................................................................................. 91
7-18 Process ID Register....................................................................................................................91
7-19 Accessing the Debug Registers.................................................................................................. 93
7-20 Coprocessor Access Register .................................................................................................... 95
7-21 Accessing the XSC1 Performance Monitoring Registers ...........................................................96
7-22 Accessing the XSC2 Performance Monitoring Registers ...........................................................97
7-23 PWRMODE Register .................................................................................................................. 98
7-24 Clock and Power Management................................................................................................... 98
7-25 CCLKCFG Register ....................................................................................................................98
7-26 Accessing the Debug Registers.................................................................................................. 99
8-1 XSC1 Performance Monitoring Registers ................................................................................. 102
8-2 Clock Count Register (CCNT) .................................................................................................. 102
8-3 Performance Monitor Count Register (PMN0 and PMN1)........................................................ 103
8-4 Performance Monitor Control Register (CP14, register 0)........................................................ 104
8-5 Performance Monitoring Registers ........................................................................................... 106
Developer's Manual
Intel XScale® Core Developer's Manual
January, 2004
Contents
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