Intel XScale® Core Developer's Manual
Configuration
7.3
CP14 Registers
CP14 contains software debug registers, clock and power management registers and the
performance monitor registers.
All other registers are reserved in CP14. Reading and writing them yields unpredictable results.
7.3.1
Performance Monitoring Registers
There are two variants of the performance monitoring facility; the number, location and definition
of the registers are different between them. Software can determine which variant it is running on
by examining the CoreGen field of Coprocessor 15, ID Register (bits 15:13). (See
Register" on page 7-81
value of 0x2 is referred to as XSC2. The main difference between the two is that XSC1 has two
32-bit performance counters while XSC2 has four 32-bit performance counters.
7.3.1.1
XSC1 Performance Monitoring Registers
The performance monitoring unit in XSC1 contains a control register (PMNC), a clock counter
(CCNT) and two event counters (PMN0 and PMN1).The format of these registers can be found in
Chapter 8, "Performance
monitoring facility.
Opcode_2 and CRm should be zero.
Table 7-21.
Accessing the XSC1 Performance Monitoring Registers
(PMNC) Performance Monitor Control
Register
(CCNT) Clock Counter Register
(PMN0) Performance Count Register 0
(PMN1) Performance Count Register 1
96
for more details.) A CoreGen value of 0x1 is referred to as XSC1 and a
Monitoring", along with a description on how to use the performance
Description
January, 2004
CRn
CRm
Register#
Register#
Read: MRC p14, 0, Rd, c0, c0, 0
0b0000
0b0000
Write: MCR p14, 0, Rd, c0, c0, 0
Read: MRC p14, 0, Rd, c1, c0, 0
0b0001
0b0000
Write: MCR p14, 0, Rd, c1, c0, 0
Read: MRC p14, 0, Rd, c2, c0, 0
0b0010
0b0000
Write: MCR p14, 0, Rd, c2, c0, 0
Read: MRC p14, 0, Rd, c3, c0, 0
0b0011
0b0000
Write: MCR p14, 0, Rd, c3, c0, 0
Table 7-4, "ID
Instruction
Developer's Manual
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