Intel XScale Core Developer's Manual page 44

Intel XScale® Core Developer's Manual
Memory Management
The proper procedure for locking entries into the data TLB is shown in
Example 3-3. Locking Entries into the Data TLB
; R1, and R2 contain the virtual addresses to translate and lock into the data TLB
MCR P15,0,R1,C8,C6,1
MCR P15,0,R1,C10,C8,0
; Repeat sequence for virtual address in R2
MCR P15,0,R2,C8,C6,1
MCR P15,0,R2,C10,C8,0
CPWAIT
; The MMU is guaranteed to be updated at this point; the next instruction will
; see the locked data TLB entries.
Note: Care must be exercised here when allowing exceptions to occur during this routine whose handlers
may have data that lies in a page that is trying to be locked into the TLB.
44
; Invalidate the data TLB entry specified by the
; virtual address in R1
; Translate virtual address (R1) and lock into
; data TLB
; Invalidate the data TLB entry specified by the
; virtual address in R2
; Translate virtual address (R2) and lock into
; data TLB
; wait for locks to complete
January, 2004
Example 3-3 on page 3-44.
Developer's Manual