Register 5: Fault Status Register; Register 6: Fault Address Register - Intel XScale Core Developer's Manual

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Intel XScale® Core Developer's Manual
Configuration
7.2.6

Register 5: Fault Status Register

The Fault Status Register (FSR) indicates which fault has occurred, which could be either a
prefetch abort or a data abort. Bit 10 extends the encoding of the status field for prefetch aborts and
data aborts. The definition of the extended status field is found in
Architecture" on page
event is found in the debug control and status register (CP14, register 10). When bit 9 is set, the
domain and extended status field are undefined.
Upon entry into the prefetch abort or data abort handler, hardware will update this register with the
source of the exception. Software is not required to clear these fields.
Table 7-10.
Fault Status Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:11
10
9
8
7:4
3:0
7.2.7

Register 6: Fault address Register

Table 7-11.
Fault Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
86
2-32. Bit 9 indicates that a debug event occurred and the exact source of the
Access
Read-unpredictable / Write-as-Zero
Read / Write
Read / Write
Read-as-zero / Write-as-Zero
Read / Write
Read / Write
Access
Read / Write
January, 2004
Reserved
Status Field Extension (X)
This bit is used to extend the encoding of the Status field,
when there is a prefetch abort and when there is a data
abort. The definition of this field can be found in
Section 2.3.4, "Event Architecture" on page 2-32
Debug Event (D)
This flag indicates a debug event has occurred and that
the cause of the debug event is found in the MOE field of
the debug control register (CP14, register 10)
= 0
Domain - Specifies which of the 16 domains was being
accessed when a data abort occurred
Status - Type of data access being attempted
Fault Virtual Address
Fault Virtual Address - Contains the MVA of the data
access that caused the memory abort
Section 2.3.4, "Event
8
7
6
5
4
3
2
X D 0
Domain
Status
Description
8
7
6
5
4
3
2
Description
Developer's Manual
1
0
1
0

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