Register 1: Control & Auxiliary Control Registers; Arm* Control Register - Intel XScale Core Developer's Manual

7.2.2 Register 1: Control & Auxiliary Control Registers
Register 1 is made up of two registers, one that is compliant with ARM Version 5TE and referred
by opcode_2 = 0x0, and the other which is specific to the core is referred by opcode_2 = 0x1. The
latter is known as the Auxiliary Control Register.
The Exception Vector Relocation bit (bit 13 of the ARM control register) allows the vectors to be
mapped into high memory rather than their default location at address 0. This bit is readable and
writable by software. If the MMU is enabled, the exception vectors will be accessed via the usual
translation method involving the PID register (see
page 7-91) and the TLBs. To avoid automatic application of the PID to exception vector accesses,
software may relocate the exceptions to high memory.
Table 7-6.

ARM* Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:14
13
12
11
10
9
8
7
6:3
2
1
0
Developer's Manual
Access
Read-Unpredictable /
Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-Zero / Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-One / Write-as-One
Read / Write
Read / Write
Read / Write
January, 2004
Intel XScale® Core Developer's Manual
Section 7.2.13, "Register 13: Process ID" on
8
V I Z 0 R S B 1 1 1 1 C A M
Description
Reserved
Exception Vector Relocation (V).
0 = Base address of exception vectors is 0x0000,0000
1 = Base address of exception vectors is 0xFFFF,0000
Instruction Cache Enable/Disable (I)
0 = Disabled
1 = Enabled
Branch Target Buffer Enable (Z)
0 = Disabled
1 = Enabled
Reserved
ROM Protection (R)
This selects the access checks performed by the memory
management unit. See the ARM Architecture Reference
Manual for more information.
System Protection (S)
This selects the access checks performed by the memory
management unit. See the ARM Architecture Reference
Manual for more information.
Big/Little Endian (B)
0 = Little-endian operation
1 = Big-endian operation
= 0b1111
Data cache enable/disable (C)
0 = Disabled
1 = Enabled
Alignment fault enable/disable (A)
0 = Disabled
1 = Enabled
Memory management unit enable/disable (M)
0 = Disabled
1 = Enabled
Configuration
7 6 5 4 3 2 1 0
83