Configuration; Overview - Intel XScale Core Developer's Manual

Configuration

This chapter describes the System Control Coprocessor (CP15) and coprocessor 14 (CP14). CP15
configures the MMU, caches, buffers and other system attributes. CP14 contains the performance
monitor registers, clock and power management registers and the debug registers.
7.1

Overview

CP15 is accessed through MRC and MCR coprocessor instructions and allowed only in privileged
mode. Any access to CP15 in user mode or with LDC or STC coprocessor instructions will cause
an undefined instruction exception.
All CP14 registers can be accessed through MRC and MCR coprocessor instructions. LDC and
STC coprocessor instructions can only access the clock and power management registers, and the
debug registers. The performance monitoring registers can't be accessed by LDC and STC
because CRm != 0x0, which can't be expressed by LDC or STC. Access to all registers is allowed
only in privileged mode. Any access to CP14 in user mode will cause an undefined instruction
exception.
Coprocessors, CP15 and CP14, on the Intel XScale
or MCRR instructions. An attempt to access these coprocessors with these instructions will result
in an undefined instruction exception.
Many of the MCR commands available in CP15 modify hardware state sometime after execution.
A software sequence is available for those wishing to determine when this update occurs and can
be found in
The Intel XScale
(Process ID) register and associated logic. For a detailed description of this facility, see
Section 7.2.13, "Register 13: Process ID" on page
facility because, when interacting with CP15, some addresses are modified by the PID and others
are not. An address that has yet to be modified by the PID ("PIDified") is known as a virtual
address (VA). An address that has been through the PID logic, but not translated into a physical
address, is a modified virtual address (MVA).
Developer's Manual
Section 2.3.3, "Additions to CP15 Functionality" on page
®
core includes an extra level of virtual address translation in the form of a PID
January, 2004
Intel XScale® Core Developer's Manual
®
core do not support access via CDP, MRRC,
2-31.
7-91. Privileged code needs to be aware of this
Configuration
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