Memory Management; Instruction Cache; Branch Target Buffer; Data Cache - Intel XScale Core Developer's Manual

1.2.2.2

Memory Management

The Intel XScale
in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to
physical address translation.
The MMU Architecture also specifies the caching policies for the instruction cache and data
memory. These policies are specified as page attributes and include:
•
identifying code as cacheable or non-cacheable
•
selecting between the mini-data cache or data cache
•
write-back or write-through data caching
•
enabling data write allocation policy
•
and enabling the write buffer to coalesce stores to external memory
Chapter 3, "Memory Management"
1.2.2.3

Instruction Cache

The Intel XScale
determined by the ASSP. The instruction cache is 32-way set associative and has a line size of
32 bytes. All requests that "miss" the instruction cache generate a 32-byte read request to external
memory. A mechanism to lock critical code within the cache is also provided.
Chapter 4, "Instruction Cache"
1.2.2.4

Branch Target Buffer

The Intel XScale
type instructions. It provides storage for the target address of branch type instructions and predicts
the next address to present to the instruction cache when the current instruction address is that of a
branch.
The BTB holds 128 entries. See
1.2.2.5

Data Cache

The Intel XScale
by the ASSP. Besides the main data cache, a mini-data cache is provided whose size is 1/16
main data cache. So a 32 K, 16 K byte main data cache would have a 2 K, 1 K byte mini-data cache
respectively. The main data cache is 32-way set associative and the mini-data cache is 2-way set
associative. Each cache has a line size of 32 bytes, supports write-through or write-back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by
coprocessor 15.
Chapter 6, "Data Cache"
The Intel XScale
RAM. Software may place special tables or frequently used variables in this RAM. See
Section 6.4, "Re-configuring the Data Cache as Data RAM" on page 6-71
this.
Developer's Manual
®
core implements the Memory Management Unit (MMU) Architecture specified
discusses this in more detail.
®
core comes with either a 16 K or 32 K byte instruction cache. The size is
discusses this in more detail.
®
core provides a Branch Target Buffer (BTB) to predict the outcome of branch
Chapter 5, "Branch Target Buffer"
®
core comes with either a 16 K or 32 K byte data cache. The size is determined
discusses all this in more detail.
®
core allows applications to re-configure a portion of the data cache as data
January, 2004
Intel XScale® Core Developer's Manual
for more details.
for more information on
Introduction
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