Examples; Xsc1 Example (2 Counter Variant) - Intel XScale Core Developer's Manual

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8.6

Examples

The same example is shown below for both variants (XSC1 and XSC2).
8.6.1

XSC1 Example (2 counter variant)

In this example, the events selected with the Instruction Cache Efficiency mode are monitored and
CCNT is used to measure total execution time. Sampling time ends when PMN0 overflows which
will generate an IRQ interrupt.
Example 8-1. Configuring the Performance Monitor
; Configure PMNC with the following values:
;
evtCount0 = 7, evtCount1 = 0instruction cache efficiency
;
inten = 0x7set all counters to trigger an interrupt on
;
C = 1
;
P = 1
;
E = 1
MOV
R0,#0x7777
MCR
P14,0,R0,C0,c0,0; write R0 to PMNC
; Counting begins
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
Example 8-2. Interrupt Handling
IRQ_INTERRUPT_SERVICE_ROUTINE:
; Assume that performance counting interrupts are the only IRQ in the system
MRC
P14,0,R1,C0,c0,0; read the PMNC register
BIC
R2,R1,#1
MCR
P14,0,R2,C0,c0,0; clear interrupt flag and disable counting
MRC
P14,0,R3,C1,c0,0; read CCNT register
MRC
P14,0,R4,C2,c0,0; read PMN0 register
MRC
P14,0,R5,C3,c0,0; read PMN1 register
<process the results>
SUBS PC,R14,#4
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
Example 8-3. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI was 2.4.
Developer's Manual
overflow
reset CCNT register
reset PMN0 and PMN1 registers
enable counting
; clear the enable bit
; return from interrupt
January, 2004
Intel XScale® Core Developer's Manual
Performance Monitoring
119

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