Xsc1 Register Description (2 Counter Variant); Clock Counter (Ccnt; Cp14 - Register 1); Xsc1 Performance Monitoring Registers; Clock Count Register (Ccnt) - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Performance Monitoring
8.2

XSC1 Register Description (2 counter variant)

Table 8-1
instructions.
Table 8-1.

XSC1 Performance Monitoring Registers

(PMNC) Performance Monitor Control
Register
(CCNT) Clock Counter Register
(PMN0) Performance Count Register 0
(PMN1) Performance Count Register 1
8.2.1

Clock Counter (CCNT; CP14 - Register 1)

The format of CCNT is shown in
Monitor Control Register (PMNC) or can be set to a predetermined value by directly writing to it.
It counts core clock cycles. When CCNT reaches its maximum value 0xFFFF,FFFF, the next clock
cycle will cause it to roll over to zero and set the overflow flag (bit 6) in PMNC. An IRQ or FIQ
will be reported if it is enabled via bit 6 in the PMNC register.
Table 8-2.

Clock Count Register (CCNT)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
102
contains details on accessing these registers with MRC and MCR coprocessor
Description
Table
Access
Read / Write
January, 2004
CRn CRm
Register# Register#
0b0000 0b0000
0b0001 0b0000
0b0010 0b0000
0b0011 0b0000
8-6. The clock counter is reset to '0' by Performance
Clock Counter
32-bit clock counter - Reset to '0' by PMNC register.
When the clock counter reaches its maximum value
0xFFFF,FFFF, the next cycle will cause it to roll over to
zero and generate an IRQ or FIQ if enabled.
Instruction
Read: MRC p14, 0, Rd, c0, c0, 0
Write: MCR p14, 0, Rd, c0, c0, 0
Read: MRC p14, 0, Rd, c1, c0, 0
Write: MCR p14, 0, Rd, c1, c0, 0
Read: MRC p14, 0, Rd, c2, c0, 0
Write: MCR p14, 0, Rd, c2, c0, 0
Read: MRC p14, 0, Rd, c3, c0, 0
Write: MCR p14, 0, Rd, c3, c0, 0
8 7 6 5 4 3 2
Description
Developer's Manual
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