Rf (Register File / Shifter) Pipestage; X1 (Execute) Pipestages; X2 (Execute 2) Pipestage; Wb (Write-Back) - Intel XScale Core Developer's Manual

A.2.3.3.

RF (Register File / Shifter) Pipestage

The main function of the RF pipestage is to read and write to the register file unit, or RFU. It
provides source data to:
•
EX for ALU operations
•
MAC for multiply operations
•
Data Cache for memory writes
•
Coprocessor interface
The ID unit decodes the instruction and specifies which registers are accessed in the RFU. Based
upon this information, the RFU determines if it needs to stall the pipeline due to a register
dependency. A register dependency occurs when a previous instruction is about to modify a
register value that has not been returned to the RFU and the current instruction needs to access that
same register. If no dependencies exist, the RFU will select the appropriate data from the register
file and pass it to the next pipestage. When a register dependency does exist, the RFU will keep
track of which register is unavailable and when the result is returned, the RFU will stop stalling the
pipe.
The ARM architecture specifies that one of the operands for data processing instructions as the
shifter operand, where a 32-bit shift can be performed before it is used as an input to the ALU. This
shifter is located in the second half of the RF pipestage.
A.2.3.4.

X1 (Execute) Pipestages

The X1 pipestage performs the following functions:
•
ALU calculation - the ALU performs arithmetic and logic operations, as required for data
processing instructions and load/store index calculations.
•
Determine conditional instruction execution - The instruction's condition is compared to the
CPSR prior to execution of each instruction. Any instruction with a false condition is
cancelled, and will not cause any architectural state changes, including modifications of
registers, memory, and PSR.
•
Branch target determination - If a branch was mispredicted by the BTB, the X1 pipestage
flushes all of the instructions in the previous pipestages and sends the branch target address to
the BTB, which will restart the pipeline
A.2.3.5.

X2 (Execute 2) Pipestage

The X2 pipestage contains the program status registers (PSRs). This pipestage selects what is
going to be written to the RFU in the WB cycle: PSRs (MRS instruction), ALU output, or other
items.
A.2.3.6.

WB (write-back)

When an instruction has reached the write-back stage, it is considered complete. Changes are
written to the RFU.
Developer's Manual
Intel XScale® Core Developer's Manual
January, 2004
Optimization Guide
181