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Intel XScale® Core Developer's Manual
Programming Model
2.2.4
ARM DSP-Enhanced Instruction Set
The Intel XScale
instructions that boost the performance of signal processing applications. There are new multiply
instructions that operate on 16-bit data values and new saturation instructions. Some of the new
instructions are:
•
SMLAxy
•
SMLAWy
•
SMLALxy
•
SMULxy
•
SMULWy
•
QADD
•
QDADD
•
QSUB
•
QDSUB
The Intel XScale
implementation notes:
•
PLD is interpreted as a read operation by the MMU and is ignored by the data breakpoint unit
(i.e., PLD will never generate data breakpoint events).
•
PLD to a non-cacheable page performs no action. Also, if the targeted cache line is already
resident, this instruction has no affect.
•
Both LDRD and STRD instructions will generate an alignment exception when the address
bits [2:0] = 0b100.
MCRR and MRRC are only supported on the Intel XScale
and are used to access the internal accumulator. See
to coprocessors 15 and 14 generate an undefined instruction exception. Refer to the Intel XScale
core implementation option section of the ASSP architecture specification for the behavior when
accessing all other coprocessors.
2.2.5
Base Register Update
If a data abort is signalled on a memory instruction that specifies writeback, the contents of the
base register will not be updated. This holds for all load and store instructions. This behavior
matches that of the first generation StrongARM processor and is referred to in the ARM V5TE
architecture as the Base Restored Abort Model.
22
®
core implements the ARM DSP-enhanced instruction set which is a set of
32<=16x16+32
32<=32x16+32
64<=16x16+64
32<=16x16
32<=32x16
adds two registers and saturates the result if an overflow occurred
doubles and saturates one of the input registers then add and saturate
subtracts two registers and saturates the result if an overflow occurred
doubles and saturates one of the input registers then subtract and saturate
®
core also implements LDRD, STRD and PLD instructions with the following
January, 2004
®
core when directed to coprocessor 0
Section 2.3.1.2
for more information. Access
Developer's Manual
®
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