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This mode is used when Intel
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
Figure 3.
Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one DIMM connector
per channel.For dual-channel modes both channels must have an DIMM connector
populated and for single-channel mode only a single-channel must have an DIMM
connector populated.
2.1.5
Technology Enhancements of Intel
®
(Intel
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel
2.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
18
®
Flex Memory Technology is disabled and both Channel A
Dual Channel Interleaved
(memory sizes must match)
CL
Top of
Memory
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
0
FMA)
®
FMA technology enhancements.
Dual Channel Asymmetric
(memory sizes can differ)
CL
CH. A
CH. B
®
Fast Memory Access
®
®
Celeron
Processor P4505, U3405 Series
Document Number: 323178-003
Interfaces
Top of
Memory
CH.B-top
DRB
0
August 2010
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