J3C2/J3C1- Dual Channel Lvds Data Connector; Table 16. J3B1- Tpm Pin Header; Table 17. J4C2-Lvds Backlight Control Connector - Intel QM77 User Manual

Table 16. J3B1- TPM Pin Header

Pin
1
3
5
7
9
11
13
15
17
19
Recommended TPM: Nuvoton NPCT42x

Table 17. J4C2-LVDS Backlight Control Connector

Pin
1
2
3
4
V12: Backlight Power (12V)
L_BKLT_CTL: Backlight Control (voltage amplitude is between 0V-3.3V while the duty
L_BKLTEN: Backlight Enable (Active High)
4.1.3.1

J3C2/J3C1- Dual Channel LVDS Data Connector

This Development Kit provides one dual-channel 24bit LVDS connector.
 LVDS 1: J3C2
 LVDS 2: J3C1
If single channel 18-bit LVDS screens are adopted, the LVDS data cable must connect
to LVDS 1 only.
Note: LVDSA_X indicates to dual scan the odd line while LVDSB_X indicates to dual scan the
even line.
Intel® Core™ i5-3610ME Processor (PGA) and Mobile Intel® QM77 Express Chipset Development Kit
User Guide
20
Signal Name
CLOCK
LPC_FRAME-
PLT_RST-
LPC_AD3
V3P3
LPC_AD0
SMB_CLK
V3P3_A
GND
SUS_SATA-
V12
L_BKLT_CTL
L_BKLTEN
GND
cycle is between 0% ~ 100%)
Pin Signal Name
2 GND
4 NC
6 V5
8 LPC_AD2
10 LPC_AD1
12 GND
14 SMB_DATA
16 SERIRQ
18 CLKRUN
20 LPC_DRQ0-
Signal Name
Document Number: 328076-001
Reference Board Summary
November 2012