Data Signals; Strobe Signals; Href Generation/Distribution; Single Hub Interface Reference Divider Circuit - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
2.8.1

Data Signals

The Hub interface data signals (HL[10:0]) should be routed 5 on 20. These signals can be routed 5
on 15 for navigation around components or mounting holes. In order to break-out of the MCH
uBGA and the ICH uBGA, the hub interface data signals can be routed 5 on 5. The signals must be
separated to 5 on 20 within 300 mil of the uBGA package.
The maximum trace length for the hub interface data signals is 7". These signals must each be
matched within ±0.1" of the HL_STB and HL_STB# signals.
2.8.2

Strobe Signals

Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20
mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The
maximum length for the strobe signals is 7" and the two strobes must be the same length.
Additionally, the trace length for each data signal must be matched to the trace length of the strobes
with ±0.1".
2.8.3

HREF Generation/Distribution

HREF is the hub interface reference voltage. It is 0.5 * 1.8V = 0.9V ±2%. It can be generated using
a single HREF divider or locally generated dividers (as shown in
The resistors should be equal in value and rated at 1% tolerance (to maintain 2% tolerance on
0.9V). The value of these resistors must be chosen to ensure that the reference voltage tolerance is
maintained over the entire input leakage specification. The recommended range for the resistor
value is from minimum 100 ohm to maximum 1K ohm (300 ohm shown in example).
The single HREF divider should not be located more than 4" away from either MCH or ICH. If the
single HREF divider is located more than 4" away, then the locally generated hub interface
reference dividers should be used instead.
The reference voltage generated by a single HREF divider should be bypassed to ground at each
component with a 0.01 uF capacitor located close to the component HREF pin. If the reference
voltage is generated locally, the bypass capacitor needs to be close to the component HREF pin.
Figure 2-34. Single Hub Interface Reference Divider Circuit
2-44
1.8V
300Ω
HUBREF
0.01uF
MCH
300Ω
HubRef1.vsd
Figure 2-34 and
HUBREF
0.01uF
ICH
0.1uF
®
Intel 820 Chipset Design Guide
Figure 2-35).