Single-Slot At 133 Mhz; Single-Slot Point-To-Point Topology; Pci-X 133 Mhz Single Slot Routing Recommendations - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
6.4.2

Single-Slot at 133 MHz

Figure 17
single-slot connector CONN1 through TL1 line segment to the 80331.
P
Figure 17.

Single-Slot Point-to-Point Topology

Table 9.

PCI-X 133 MHz Single Slot Routing Recommendations

Parameter
Reference Plane
Preferred Layer
Breakout
Motherboard Impedance (for
both microstrip and stripline)
Add-in card Impedance (for
both microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Trace Length 1 (TL1): From
80331 signal Ball to first
junction
Trace Length 2 (TL_AD1)-
from connector to receiver
Length Matching
Requirements:
Number of vias
48
shows one of the chipset PCI AD lines connected through TL_AD1 line segments to a
Routing Guideline for Lower AD Bus Routing Guideline for Upper AD Bus
Route over an unbroken ground plane
Stripline
5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils.
50 ohms +/- 15%
57 ohms +/- 15%
12 mils from edge to edge
18 mils from edge to edge
Spacing from other groups: 25 mils minimum edge to edge
2.25" minimum - 7.5" maximum
0.75" minimum - 1.5" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Two vias maximum
AD1
CONN1
TL1
1.25" minimum - 6.75" maximum
1.75" minimum - 2.75" maximum
Table 8.