Single-Ended Clocking Bsel[1:0] Implementation; Differential Host Bus Clocking Routing; Single Ended Clock Bsel Circuit; Clkref Component Values - Intel Pentium III Design Manual

Table 4-3. CLKREF Component Values
Reference
R1
R2
C1
4.2.2

Single-Ended Clocking BSEL[1:0] Implementation

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In an Intel Pentium III Processor with 512KB L2 Cache platform that is using single-ended (SE)
clocking or a clock source that does not support the VTT_PWRGD protocol, the normal BSEL frequency
selection process will not work. Since the clock generator is not compatible with dynamic BSEL
assertions, all BSEL[1:0] signals should not be connected together. Instead, the BSEL pins on the clock
generator should be pulled-up to 3.3 V through a 1 KΩ, 5% resistor. This strapping will force the clock
generator into 133 MHz clocking mode and will only support 133 MHz capable processors.
Figure 4-5. Single Ended Clock BSEL Circuit
4.3

Differential Host Bus Clocking Routing

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Intel Pentium III Processor with 512KB L2 Cache dual-processor platforms support differential host
bus clock drivers. When operating in differential clocking mode, the BCLK and BCLK#/CLKREF form a
differential pair of clock inputs. The differential pair of traces should be routed with special care and using
standard differential signalling techniques. The following sections contain the recommended topology
and routing for differential clocking for these platforms.
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Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
150 Ω
150 Ω
4.7 µF
NC NC
BSEL0 BSEL1
Processor 1
Value
3.3V
1KΩ
5%
NC NC
BSEL0
BSEL0 BSEL1
Clock Driver
Processor 0
Notes
1% Tolerance
1% Tolerance
3.3V
1KΩ
5%
BSEL1
4-5