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Epson S1C17W23 Manuals
Manuals and User Guides for Epson S1C17W23. We have
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Epson S1C17W23 manual available for free PDF download: Technical Manual
Epson S1C17W23 Technical Manual (354 pages)
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
Brand:
Epson
| Category:
Microcontrollers
| Size: 10.2 MB
Table of Contents
Notational Conventions and Symbols in this Manual
3
Table of Contents
4
Overview
15
Features
15
Block Diagram
17
Pins
19
Pin Configuration Diagram (TQFP15-128PIN)
19
Pad Configuration Diagram (Chip)
21
Pin Descriptions
23
Power Supply, Reset, and Clocks
28
Power Generator (PWG2)
28
Overview
28
Pins
28
Operations
29
System Reset Controller (SRC)
31
Overview
31
Input Pin
31
Reset Sources
31
Initialization Conditions (Reset Groups)
32
Clock Generator (CLG)
33
Overview
33
Input/Output Pins
34
Clock Sources
34
Operations
36
Operating Mode
41
Initial Boot Sequence
41
Transition between Operating Modes
41
Interrupts
43
Control Registers
43
PWG2 Control Register
43
PWG2 Timing Control Register
44
PWG2 Interrupt Flag Register
44
PWG2 Interrupt Enable Register
44
CLG System Clock Control Register
44
CLG Oscillation Control Register
46
CLG IOSC Control Register
46
CLG OSC1 Control Register
47
CLG OSC3 Control Register
48
CLG Interrupt Flag Register
49
CLG Interrupt Enable Register
50
CLG FOUT Control Register
51
CPU and Debugger
52
Overview
52
CPU Core
53
CPU Registers
53
Instruction Set
53
Reading PSR
53
I/O Area Reserved for the S1C17 Core
53
Debugger
53
Debugging Functions
53
Resource Requirements and Debugging Tools
54
List of Debugger Input/Output Pins
54
External Connection
54
Flash Security Function
55
Control Register
55
MISC PSR Register
55
Debug RAM Base Register
56
Memory and Bus
57
Overview
57
Bus Access Cycle
58
Flash Memory
58
Flash Memory Pin
58
Flash Bus Access Cycle Setting
59
Flash Programming
59
Ram
59
Display Data RAM
59
Peripheral Circuit Control Registers
59
System-Protect Function
64
Control Registers
64
MISC System Protect Register
64
MISC IRAM Size Register
65
FLASHC Flash Read Cycle Register
65
Interrupt Controller (ITC)
66
Overview
66
Vector Table
66
Vector Table Base Address (TTBR)
68
Initialization
68
Maskable Interrupt Control and Operations
68
Peripheral Circuit Interrupt Control
68
ITC Interrupt Request Processing
69
Conditions to Accept Interrupt Requests by the CPU
69
Nmi
69
Software Interrupts
69
Interrupt Processing by the CPU
70
Control Registers
70
MISC Vector Table Address Low Register
70
MISC Vector Table Address High Register
70
ITC Interrupt Level Setup Register X
70
O Ports (PPORT)
73
Overview
73
I/O Cell Structure and Functions
74
Schmitt Input
74
Over Voltage Tolerant Fail-Safe Type I/O Cell
74
Pull-Up/Pull-Down
74
CMOS Output and High Impedance State
75
Clock Settings
75
PPORT Operating Clock
75
Clock Supply in SLEEP Mode
75
Clock Supply in DEBUG Mode
75
Operations
75
Initialization
75
Port Input/Output Control
77
Interrupts
78
Control Registers
78
Px Port Data Register
78
Px Port Enable Register
79
Px Port Pull-Up/Down Control Register
79
Px Port Interrupt Flag Register
80
Px Port Interrupt Control Register
80
Px Port Chattering Filter Enable Register
80
Px Port Mode Select Register
80
Px Port Function Select Register
81
P Port Clock Control Register
81
P Port Interrupt Flag Group Register
82
Control Register and Port Function Configuration of this IC
83
P0 Port Group
83
P1 Port Group
84
P2 Port Group
85
P3 Port Group
86
P4 Port Group
87
Pd Port Group
88
Common Registers between Port Groups
89
Universal Port Multiplexer (UPMUX)
90
Overview
90
Peripheral Circuit I/O Function Assignment
90
Control Registers
91
Pxy-Xz Universal Port Multiplexer Setting Register
91
Watchdog Timer (WDT)
92
Overview
92
Clock Settings
92
WDT Operating Clock
92
Clock Supply in DEBUG Mode
93
Operations
93
WDT Control
93
Operations in HALT and SLEEP Modes
93
Control Registers
94
WDT Clock Control Register
94
WDT Control Register
94
Real-Time Clock (RTCA)
96
Overview
96
Output Pin and External Connection
96
Output Pin
96
Clock Settings
97
RTCA Operating Clock
97
Theoretical Regulation Function
97
Operations
98
RTCA Control
98
Real-Time Clock Counter Operations
99
Stopwatch Control
99
Stopwatch Count-Up Pattern
99
Interrupts
100
Control Registers
101
RTC Control Register
101
RTC Second Alarm Register
102
RTC Hour/Minute Alarm Register
103
RTC Stopwatch Control Register
103
RTC Second/1Hz Register
104
RTC Hour/Minute Register
105
RTC Month/Day Register
106
RTC Year/Week Register
106
RTC Interrupt Flag Register
107
RTC Interrupt Enable Register
108
Supply Voltage Detector (SVD)
110
Overview
110
Input Pin and External Connection
111
Input Pin
111
External Connection
111
Clock Settings
111
SVD Operating Clock
111
Clock Supply in SLEEP Mode
111
Clock Supply in DEBUG Mode
112
Operations
112
SVD Control
112
SVD Operations
113
SVD Interrupt and Reset
113
SVD Interrupt
113
SVD Reset
114
Control Registers
114
SVD Clock Control Register
114
SVD Control Register
115
SVD Status and Interrupt Flag Register
116
SVD Interrupt Enable Register
117
16-Bit Timers (T16)
118
Overview
118
Input Pin
118
Clock Settings
119
T16 Operating Clock
119
Clock Supply in SLEEP Mode
119
Clock Supply in DEBUG Mode
119
Event Counter Clock
119
Operations
119
Initialization
119
Counter Underflow
120
Operations in Repeat Mode
120
Operations in One-Shot Mode
120
Counter Value Read
121
Interrupt
121
Control Registers
121
T16 Ch.n Clock Control Register
121
T16 Ch.n Mode Register
122
T16 Ch.n Control Register
122
T16 Ch.n Reload Data Register
123
T16 Ch.n Counter Data Register
123
T16 Ch.n Interrupt Flag Register
123
T16 Ch.n Interrupt Enable Register
124
Uart (Uart)
125
Overview
125
Input/Output Pins and External Connections
126
List of Input/Output Pins
126
External Connections
126
Input Pin Pull-Up Function
126
Output Pin Open-Drain Output Function
126
Clock Settings
126
UART Operating Clock
126
Clock Supply in SLEEP Mode
126
Clock Supply in DEBUG Mode
127
Baud Rate Generator
127
Data Format
127
Operations
128
Initialization
128
Data Transmission
128
Data Reception
129
Irda Interface
130
Receive Errors
131
Framing Error
131
Parity Error
132
Overrun Error
132
Interrupts
132
Control Registers
132
UART Ch.n Clock Control Register
132
UART Ch.n Mode Register
133
UART Ch.n Baud-Rate Register
134
UART Ch.n Control Register
134
UART Ch.n Transmit Data Register
135
UART Ch.n Receive Data Register
135
UART Ch.n Status and Interrupt Flag Register
135
Synchronous Serial Interface (SPIA)
138
Overview
138
Input/Output Pins and External Connections
139
List of Input/Output Pins
139
External Connections
139
Pin Functions in Master Mode and Slave Mode
140
Input Pin Pull-Up/Pull-Down Function
140
Clock Settings
140
SPIA Operating Clock
140
Clock Supply in DEBUG Mode
141
SPI Clock (Spiclkn) Phase and Polarity
141
Data Format
142
Operations
142
Initialization
142
Data Transmission in Master Mode
142
Data Reception in Master Mode
144
Terminating Data Transfer in Master Mode
145
Data Transfer in Slave Mode
145
Terminating Data Transfer in Slave Mode
147
Interrupts
147
Control Registers
148
SPIA Ch.n Mode Register
148
SPIA Ch.n Control Register
149
SPIA Ch.n Transmit Data Register
150
SPIA Ch.n Receive Data Register
150
SPIA Ch.n Interrupt Flag Register
150
SPIA Ch.n Interrupt Enable Register
151
C (I2C)
152
Overview
152
Input/Output Pins and External Connections
153
List of Input/Output Pins
153
External Connections
153
Clock Settings
154
I2C Operating Clock
154
Clock Supply in DEBUG Mode
154
Baud Rate Generator
154
Operations
155
Initialization
155
Data Transmission in Master Mode
156
Data Reception in Master Mode
158
10-Bit Addressing in Master Mode
160
Data Transmission in Slave Mode
161
Data Reception in Slave Mode
163
Slave Operations in 10-Bit Address Mode
165
Automatic Bus Clearing Operation
165
Error Detection
166
Interrupts
167
Control Registers
168
I2C Ch.n Clock Control Register
168
I2C Ch.n Mode Register
169
I2C Ch.n Baud-Rate Register
169
I2C Ch.n Own Address Register
169
I2C Ch.n Control Register
170
I2C Ch.n Transmit Data Register
171
I2C Ch.n Receive Data Register
171
I2C Ch.n Status and Interrupt Flag Register
171
I2C Ch.n Interrupt Enable Register
172
16-Bit PWM Timers (T16B)
174
Overview
174
Input/Output Pins
175
Clock Settings
176
T16B Operating Clock
176
Clock Supply in SLEEP Mode
176
Clock Supply in DEBUG Mode
176
Event Counter Clock
176
Operations
177
Initialization
177
Counter Block Operations
178
Comparator/Capture Block Operations
181
TOUT Output Control
189
Interrupt
195
Control Registers
195
T16B Ch.n Clock Control Register
195
T16B Ch.n Counter Control Register
196
T16B Ch.n Max Counter Data Register
197
T16B Ch.n Timer Counter Data Register
197
T16B Ch.n Counter Status Register
198
T16B Ch.n Interrupt Flag Register
199
T16B Ch.n Interrupt Enable Register
200
T16B Ch.n Comparator/Capture M Control Register
201
T16B Ch.n Compare/Capture M Data Register
203
Sound Generator (SNDA)
204
Overview
204
Output Pins and External Connections
205
List of Output Pins
205
Output Pin Drive Mode
205
External Connections
205
Clock Settings
206
SNDA Operating Clock
206
Clock Supply in SLEEP Mode
206
Clock Supply in DEBUG Mode
206
Operations
206
Initialization
206
Buzzer Output in Normal Buzzer Mode
206
Buzzer Output in One-Shot Buzzer Mode
209
Output in Melody Mode
210
Interrupts
212
Control Registers
212
SNDA Clock Control Register
212
SNDA Select Register
213
SNDA Control Register
214
SNDA Data Register
214
SNDA Interrupt Flag Register
215
SNDA Interrupt Enable Register
216
IR Remote Controller (REMC)
217
Overview
217
Output Pin and External Connections
217
Output Pin
217
External Connections
218
Clock Settings
218
REMC Operating Clock
218
Clock Supply in SLEEP Mode
218
Clock Supply in DEBUG Mode
218
Operations
218
Initialization
218
Data Transmission Procedures
219
REMO Output Waveform
219
Continuous Data Transmission and Compare Buffers
221
Interrupts
222
Application Example: Driving el Lamp
223
Control Registers
223
REMC Clock Control Register
223
REMC Data Bit Counter Control Register
224
REMC Data Bit Counter Register
225
REMC Data Bit Active Pulse Length Register
226
REMC Data Bit Length Register
226
REMC Status and Interrupt Flag Register
226
REMC Interrupt Enable Register
227
REMC Carrier Waveform Register
227
REMC Carrier Modulation Control Register
227
LCD Driver (LCD24A)
229
Overview
229
Output Pins and External Connections
230
List of Output Pins
230
External Connections
230
Clock Settings
230
LCD24A Operating Clock
230
Clock Supply in SLEEP Mode
231
Clock Supply in DEBUG Mode
231
Frame Frequency
231
LCD Power Supply
233
Internal Generation Mode
233
External Voltage Application Mode 1
234
LCD Voltage Regulator Settings
234
LCD Voltage Booster Setting
234
LCD Contrast Adjustment
235
Operations
235
Initialization
235
Display On/Off
235
Inverted Display
236
Drive Duty Switching
236
Drive Waveforms
237
Partial Common Output Drive
241
N-Segment-Line Inverse AC Drive
241
Display Data RAM
241
Display Area Selection
241
Segment Pin Assignment
242
Common Pin Assignment
242
Interrupt
250
Control Registers
250
LCD24A Clock Control Register
250
LCD24A Control Register
251
LCD24A Timing Control Register 1
251
LCD24A Timing Control Register 2
252
LCD24A Power Control Register
252
LCD24A Display Control Register
253
LCD24A COM Pin Control Registers 0 and 1
254
LCD24A Interrupt Flag Register
254
LCD24A Interrupt Enable Register
255
F Converter (RFC)
256
Overview
256
Input/Output Pins and External Connections
257
List of Input/Output Pins
257
External Connections
257
Clock Settings
258
RFC Operating Clock
258
Clock Supply in SLEEP Mode
258
Clock Supply in DEBUG Mode
258
Operations
258
Initialization
258
Operating Modes
259
RFC Counters
259
Converting Operations and Control Procedure
260
CR Oscillation Frequency Monitoring Function
262
Interrupts
262
Control Registers
263
RFC Ch.n Clock Control Register
263
RFC Ch.n Control Register
263
RFC Ch.n Oscillation Trigger Register
264
RFC Ch.n Measurement Counter Low and High Registers
265
RFC Ch.n Time Base Counter Low and High Registers
265
RFC Ch.n Interrupt Flag Register
266
RFC Ch.n Interrupt Enable Register
266
12-Bit A/D Converter (ADC12A)
267
Overview
267
Input Pins and External Connections
268
List of Input Pins
268
External Connections
268
Clock Settings
268
ADC12A Operating Clock
268
Sampling Time
268
Operations
269
Initialization
269
Conversion Start Trigger Source
269
Conversion Mode and Analog Input Pin Settings
270
A/D Conversion Operations and Control Procedures
270
Interrupts
272
Control Registers
272
ADC12A Ch.n Control Register
272
ADC12A Ch.n Trigger/Analog Input Select Register
273
ADC12A Ch.n Configuration Register
274
ADC12A Ch.n Interrupt Flag Register
275
ADC12A Ch.n Interrupt Enable Register
276
ADC12A Ch.n Result Register M
276
Operational Amplifier/Comparator (OPCMP)
277
Overview
277
Input/Output Pins
277
Operations
278
Control Registers
278
OPCMP Mode Register
278
OPCMP Ch.n Control Register
278
Multiplier/Divider (COPRO2)
280
Overview
280
Operation Mode and Output Mode
280
Multiplication
281
Division
282
Mac
284
Reading Operation Results
286
Current Consumption
288
System Reset Controller (SRC) Characteristics
290
Clock Generator (CLG) Characteristics
290
UART (UART) Characteristics
295
Synchronous Serial Interface (SPIA) Characteristics
296
I 2 C (I2C) Characteristics
297
LCD Driver (LCD24A) Characteristics
297
R/F Converter (RFC) Characteristics
302
Basic External Connection Diagram
306
Package
309
Appendix A List of Peripheral Circuit Control Registers
310
0X41B0 Flash Controller (FLASHC)
316
0X4200-0X42E2 I/O Ports (PPORT)
316
0X4300-0X431E Universal Port Multiplexer (UPMUX)
320
0X43C0-0X43D2 I
324
C (I2C)
324
Appendix B Power Saving
339
Operating Status Configuration Examples for Power Saving
339
Other Power Saving Methods
340
Appendix C Mounting Precautions
341
Appendix D Measures against Noise
343
Revision History
346
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