Board Features - Xilinx Virtex-6 FPGA ML605 Getting Started

Getting Started with the Flash Demonstration

Board Features

The ML605 board features are shown in
are shown in
X-Ref Target - Figure 1-1
GPIO LEDs
GPIO DIP
Switch
(SW1)
MGT Clock
(J30 & J31)
USB to UART
(J21)
USB JTAG
(J22)
Ethernet
DVI Output
BPI Flash
(U4)
X-Ref Target - Figure 1-2
Ethernet GMII
J66: Shunt over 1–2
J67: Shunt over 1–2
J68: No jumper
FMC Bypass
J18: Shunt over 1–2 (Bypass FMC LPC)
J17: Shunt over 1–2 (Bypass FMC HPC)
Note: These are the JTAG chain bypasses for
the FMC LPC and FMC HPC connectors.
System Monitor
J19: Shunt over 1–2
J35: Shunt over 9–11 and
shunt over 10–12
SFP
J54: Shunt over 1–2 (Full BW)
J65: Shunt over 1–2 (SFP Enable)
PCIe Lane Size Select
J42: Shunt over 1–2
System ACE CF Error LED
J69: Shunt over 1–2
10
Figure 1-2.
User Clock Configuration
SFP DDR3 (J55-J58) Mode Switch
FMC FMC
(LPC) (HPC)
Platform Flash MGT Port
(U27) (J26-J29)
X8 PCI Express
Figure 1-1: Virtex-6 FGPA ML605 Board Features
J18
SW1
J54
J65
J66
J67
J68
S1:
4 ON (SysACE Mode = 1)
3 OFF (SysACE Addr 2 = 0)
2 OFF (SysACE Addr 1 = 0)
1 OFF (SysACE Addr 0 = 0)
Figure 1-2: Default Jumper and Switches Settings
www.xilinx.com
Figure 1-1. The default switch and jumper settings
USB 2.0
(Host)
System ACE 12V Wall Power
Address
Pushbuttons
(SW5-SW9)
16x2 LCD Character
Display
J19
J42
S2:
6 OFF (FLASH_A23 = 0)
5 OFF (M2 = 0)
4 ON (M1 = 1)
3 OFF (M0 = 0)
2 ON (CS_SEL = 1)
1 OFF (EXT_CCLK = 0)
12V ATX Power
USB 2.0
(Device)
System ACE
Prog
(SW4)
System ACE RST
(SW3)
CPU RST
(SW10)
PMBus Controller
System Monitor
Headers
PMBus
(J3)
UG533_01_01_121709
J17
S2 S1
J35
SW1:
8 OFF
7 OFF
6 OFF
5 OFF
4 OFF
3 OFF
2 OFF
UG533_01_02_121709
1 OFF
Virtex-6 Getting Started Guide
UG533 (v1.4) November 15, 2010
J69