Uart0 (Mio 18-19) - Xilinx ZCU104 User Manual

The nets of the three UART channel are level-shifted by U161. The UART connections from
XCZU7EV MPSoC U1 PL-side bank 28 to the FT4232HL device through U161 are listed in
Table 3-18.
Table 3-18: XCZU7EV U1 PL-side to FT4232HL U151 Connections via L/S U161
XCZU7EV (U1) Pin
A20
C19
C18
A19

UART0 (MIO 18-19)

This is the primary Zynq UltraScale+ MPSoC PS-side UART interface and is connected to the
U151 FT4232HL USB-to-Quad-UART with port assignments as listed in
UART0 is accessed through the U151 FT4232HL USB-to-Quad-UART bridge BDBUS port. The
UART connections from XCZU7EV MPSoC U1 PS-side MIO 18 and 19 to the FT4232HL device
through level-shifter U161 are listed in
Table 3-19: XCZU7EV U1 PS-side MIO 18, 19 to FT4232HL U151 Connections via L/S U161
XCZU7EG U1
Pin Name
PS_MIO18
PS_MIO19
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
Net Name
UART2_TXD_FPGA_RXD
UART2_RXD_FPGA_TXD
UART2_RTS_B
UART2_CTS_B
Table
Schematic Net Name
Pin#
F27 UART0_TXD_MIO18_RXD
B28 UART0_RXD_MIO19_TXD
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Chapter 3: Board Component Descriptions
FT4232HL U151
Pin Name
DDBUS1
DDBUS0
DDBUS2
DDBUS3
3-19.
FT4232HL U151
Pin Name
BDBUS1
BDBUS0
Pin #
52
48
53
54
Table 3-19. PS-side
Pin #
27
26
53
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