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This will cause the Spartan-3 FPGA to attach a weak pull-up to all the User I/O during
configuration.
Platform Flash Memory (15)
The Platform Flash memory can also be used to program the FPGA. The Platform Flash
memory can hold up to four configuration images which are selectable by setting the
jumpers on J25 and J31. By default, with out having any jumpers set, the Platform Flash is
pointing to the first block of the configuration address space.
The board is wired up so the Platform Flash memory can download bitstreams in Master
Serial, Slave Serial, Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes.
Using the iMPACT tool to program the Platform Flash memory, the user has the option to
select which of the four modes to use for programming the FPGA. The configuration mode
DIP switches on the board must be set to match the programming method being used by
the Platform Flash memory.
When set correctly, the Platform Flash memory will program the FPGA upon power-up or
whenever the Prog button is pressed.
Platform Flash Configuration Select (16)
The Platform Flash memory can hold up to four configuration images which are selectable
by setting the jumpers on J25 and J31. By default, without having any jumpers set, the
Platform Flash is pointing to the first block of the configuration address space.
Platform Flash Enable and Reset Control (17)
When using the Platform Flash memory to configure the FPGA, the configuration selector
jumper (J38) must be set to the FPGA_DONE (J38 1-2) or GND (J38 2-3). When set to
FPGA_DONE, the FPGA Done signal will enable the Platform Flash during configuration
and disable it when the Done pin goes high. This will also reset the Platform Flash Address
counter. If it is set to GND, then the Platform Flash will be left in an enabled state, pointing
to the next address after the current configuration data. This will allow the Platform Flash
data space to be used for data storage other than configuration data, where additional
memory will be available to be use as data after the FPGA has configured.
Done and INIT LED (18)
The INIT LED lights upon power-up to indicate that the FPGA has successfully powered
up and completed its internal power-on process.
The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted
when the FPGA is successfully configured.
Error LEDs (Active High) (19)
There are 2 red LEDs are intended to be used for signaling error conditions such as bus
errors, but can be used for any other purpose. They are active high LEDs directly
controllable by the FPGA:
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
www.xilinx.com
Detailed Description
13
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