Appendix C: Master Constraints File Listing; Ac701 Board Xdc File Listing - Xilinx AC701 User Manual

Master Constraints File Listing
TheAC701 board master Xilinx® design constraints (XDC) file template provides for
designs targeting the AC701 board. Net names in the constraints listed in the
XDC File Listing
identify the appropriate pins and replace the net names in this list with net names in the
user RTL. For more information, see UG903, Vivado Design Suite User Guide, Using
Constraints.
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface.
The FMC HPC connector J30 is connected to a 2.5V V
card implements customer-specific circuitry, the FMC bank I/O standards must be
uniquely defined by each customer.
Note:
the

AC701 Board XDC File Listing

AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
correlate with net names on the AC701 board schematic. Users must
The XDC file listed in this appendix might not be the latest version. Always refer to
Artix-7 FPGA AC701 Evaluation Kit website
#QSPI
set_property PACKAGE_PIN R14 [get_ports FLASH_D0]
set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D0]
set_property PACKAGE_PIN R15 [get_ports FLASH_D1]
set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D1]
set_property PACKAGE_PIN P14 [get_ports FLASH_D2]
set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D2]
set_property PACKAGE_PIN N14 [get_ports FLASH_D3]
set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D3]
set_property PACKAGE_PIN P18 [get_ports QSPI_IC_CS_B]
set_property IOSTANDARD LVCMOS33 [get_ports QSPI_IC_CS_B]
set_property PACKAGE_PIN P15 [get_ports CTRL2_PWRGOOD]
set_property IOSTANDARD LVCMOS33 [get_ports CTRL2_PWRGOOD]
set_property PACKAGE_PIN P16 [get_ports FPGA_EMCCLK]
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_EMCCLK]
#SDIO
set_property PACKAGE_PIN P24 [get_ports SDIO_SDDET]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDDET]
set_property PACKAGE_PIN R20 [get_ports SDIO_SDWP]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDWP]
set_property PACKAGE_PIN N23 [get_ports SDIO_CMD]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CMD]
set_property PACKAGE_PIN N24 [get_ports SDIO_CLK]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CLK]
set_property PACKAGE_PIN P19 [get_ports SDIO_DAT0]
set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT0]
set_property PACKAGE_PIN N19 [get_ports SDIO_DAT1]
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Appendix C
bank. Because each user's FMC
cco
for the latest FPGA pins constraints file.
AC701 Board
85