Appendix C: Master Constraints File Listing; Vc7222 Board Xdc Listing - Xilinx Virtex-7 VC7222 User Manual

Master Constraints File Listing
The VC7222 board master Xilinx design constraints (XDC) file template is provided for
designs targeting the VC7222 Virtex®-7 FPGA GTH and GTZ Transceiver Characterization
Board. Net names in the constraints listed below correlate with net names on the VC7222
board schematic. Users must identify the appropriate pins and replace the net names
below with net names in the user RTL. See Vivado Design Suite User Guide: Using Constraints
(UG903)

VC7222 Board XDC Listing

VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
[Ref 4] for more information.
#FMC1
set_property PACKAGE_PIN AP1
set_property IOSTANDARD
set_property PACKAGE_PIN AK2
set_property IOSTANDARD
set_property PACKAGE_PIN AL2
set_property IOSTANDARD
set_property PACKAGE_PIN AJ15
set_property IOSTANDARD
set_property PACKAGE_PIN AK15
set_property IOSTANDARD
set_property PACKAGE_PIN AK3
set_property IOSTANDARD
set_property PACKAGE_PIN AL3
set_property IOSTANDARD
set_property PACKAGE_PIN AL15
set_property IOSTANDARD
set_property PACKAGE_PIN AL14
set_property IOSTANDARD
#FMC1 LA
set_property PACKAGE_PIN AJ5
set_property IOSTANDARD
set_property PACKAGE_PIN AK5
set_property IOSTANDARD
set_property PACKAGE_PIN AJ4
set_property IOSTANDARD
set_property PACKAGE_PIN AJ3
set_property IOSTANDARD
set_property PACKAGE_PIN AG6
set_property IOSTANDARD
set_property PACKAGE_PIN AG5
set_property IOSTANDARD
set_property PACKAGE_PIN AH6
set_property IOSTANDARD
set_property PACKAGE_PIN AJ6
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[get_ports FMC1_PRSNT_M2C_L]
LVCMOS18 [get_ports FMC1_PRSNT_M2C_L]
[get_ports FMC1_CLK0_M2C_P]
LVCMOS18 [get_ports FMC1_CLK0_M2C_P]
[get_ports FMC1_CLK0_M2C_N]
LVCMOS18 [get_ports FMC1_CLK0_M2C_N]
[get_ports FMC1_CLK1_M2C_P]
LVCMOS18 [get_ports FMC1_CLK1_M2C_P]
[get_ports FMC1_CLK1_M2C_N]
LVCMOS18 [get_ports FMC1_CLK1_M2C_N]
[get_ports FMC1_CLK2_BIDIR_P]
LVDS [get_ports FMC1_CLK2_BIDIR_P]
[get_ports FMC1_CLK2_BIDIR_N]
LVDS [get_ports FMC1_CLK2_BIDIR_N]
[get_ports FMC1_CLK3_BIDIR_P]
LVCMOS18 [get_ports FMC1_CLK3_BIDIR_P]
[get_ports FMC1_CLK3_BIDIR_N]
LVCMOS18 [get_ports FMC1_CLK3_BIDIR_N]
[get_ports FMC1_LA00_CC_P]
LVCMOS18 [get_ports FMC1_LA00_CC_P]
[get_ports FMC1_LA00_CC_N]
LVCMOS18 [get_ports FMC1_LA00_CC_N]
[get_ports FMC1_LA01_CC_P]
LVCMOS18 [get_ports FMC1_LA01_CC_P]
[get_ports FMC1_LA01_CC_N]
LVCMOS18 [get_ports FMC1_LA01_CC_N]
[get_ports FMC1_LA02_P]
LVCMOS18 [get_ports FMC1_LA02_P]
[get_ports FMC1_LA02_N]
LVCMOS18 [get_ports FMC1_LA02_N]
[get_ports FMC1_LA03_P]
LVCMOS18 [get_ports FMC1_LA03_P]
[get_ports FMC1_LA03_N]
Appendix C
47
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