Appendix C: Master Constraints File Listing; Introduction; Kcu1250 Board Xdc Listing - Xilinx KCU1250 User Manual

Master Constraints File Listing

Introduction

The KCU1250 board master Xilinx design constraints (XDC) file template provides for
designs targeting the KCU1250 UltraScale FPGA GTH transceiver characterization board.
Net names in the listed constraints correlate with net names on the KCU1250 board
schematic. Users must identify the appropriate pins and replace the net names with net
names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903)
[Ref 3] for more information.
See the UltraScale FPGA
IMPORTANT:

KCU1250 Board XDC Listing

#FMC1
set_property PACKAGE_PIN E12
set_property IOSTANDARD
set_property PACKAGE_PIN H12
set_property IOSTANDARD
set_property PACKAGE_PIN G12
set_property IOSTANDARD
set_property PACKAGE_PIN E22
set_property IOSTANDARD
set_property PACKAGE_PIN E23
set_property IOSTANDARD
#FMC1 LA
set_property PACKAGE_PIN H11
set_property IOSTANDARD
set_property PACKAGE_PIN G11
set_property IOSTANDARD
set_property PACKAGE_PIN D13
set_property IOSTANDARD
set_property PACKAGE_PIN C13
set_property IOSTANDARD
set_property PACKAGE_PIN A13
set_property IOSTANDARD
set_property PACKAGE_PIN A12
set_property IOSTANDARD
KCU1250 User Guide
UG1057 (v1.0) December 19, 2014
KCU1250 characterization kit
[get_ports "FMC1_PRSNT_M2C_L"]
LVCMOS18 [get_ports "FMC1_PRSNT_M2C_L"]
[get_ports "FMC1_CLK0_M2C_P"]
LVCMOS18 [get_ports "FMC1_CLK0_M2C_P"]
[get_ports "FMC1_CLK0_M2C_N"]
LVCMOS18 [get_ports "FMC1_CLK0_M2C_N"]
[get_ports "FMC1_CLK1_M2C_P"]
LVCMOS18 [get_ports "FMC1_CLK1_M2C_P"]
[get_ports "FMC1_CLK1_M2C_N"]
LVCMOS18 [get_ports "FMC1_CLK1_M2C_N"]
[get_ports "FMC1_LA00_CC_P"]
LVCMOS18 [get_ports "FMC1_LA00_CC_P"]
[get_ports "FMC1_LA00_CC_N"]
LVCMOS18 [get_ports "FMC1_LA00_CC_N"]
[get_ports "FMC1_LA01_CC_P"]
LVCMOS18 [get_ports "FMC1_LA01_CC_P"]
[get_ports "FMC1_LA01_CC_N"]
LVCMOS18 [get_ports "FMC1_LA01_CC_N"]
[get_ports "FMC1_LA02P"]
LVCMOS18 [get_ports "FMC1_LA02P"]
[get_ports "FMC1_LA02N"]
LVCMOS18 [get_ports "FMC1_LA02N"]
www.xilinx.com
Appendix C
website for the latest XDC file.
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