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9 16-BIT TIMERS (T16)
9.3
Clock Settings
9.3.1
T16 Operating Clock
When using T16 Ch.n, the T16 Ch.n operating clock CLK_T16_n must be supplied to T16 Ch.n from the clock
generator. The CLK_T16_n supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
2. Set the following T16_nCLK register bits:
- T16_nCLK.CLKSRC[1:0] bits
- T16_nCLK.CLKDIV[3:0] bits
9.3.2
Clock Supply in SLEEP Mode
When using T16 during SLEEP mode, the T16 operating clock CLK_T16_n must be configured so that it will keep
supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_T16_n clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_T16_n clock source is 1, the CLK_T16_n clock source is deactivated
during SLEEP mode and T16 stops with the register settings and counter value maintained at those before entering
SLEEP mode. After the CPU returns to normal mode, CLK_T16_n is supplied and the T16 operation resumes.
9.3.3
Clock Supply in DEBUG Mode
The CLK_T16_n supply during DEBUG mode should be controlled using the T16_nCLK.DBRUN bit.
The CLK_T16_n supply to T16 Ch.n is suspended when the CPU enters DEBUG mode if the T16_nCLK.DBRUN
bit = 0. After the CPU returns to normal mode, the CLK_T16_n supply resumes. Although T16 Ch.n stops operat-
ing when the CLK_T16_n supply is suspended, the counter and registers retain the status before DEBUG mode
was entered. If the T16_nCLK.DBRUN bit = 1, the CLK_T16_n supply is not suspended and T16 Ch.n will keep
operating in DEBUG mode.
9.3.4
Event Counter Clock
The channel that supports the event counter function counts down at the rising edge of the EXCLm pin input signal
when the T16_nCLK.CLKSRC[1:0] bits are set to 0x3.
EXCLm pin input
Note that the EXOSC clock is selected for the channel that does not support the event counter function.
9.4
Operations
9.4.1
Initialization
T16 Ch.n should be initialized and started counting with the procedure shown below.
1. Configure the T16 Ch.n operating clock (see "T16 Operating Clock").
2. Set the T16_nCTL.MODEN bit to 1.
3. Set the T16_nMOD.TRMD bit.
4. Set the T16_nTR register.
5. Set the following bits when using the interrupt:
- Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag)
- Set the T16_nINTE.UFIE bit to 1.
9-2
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Counter
x
x - 1
Figure 9.
3.3.1 Count Down Timing
(Enable count operation clock)
(Select operation mode (Repeat mode or One-shot mode)).
(Set reload data (counter preset data))
(Enable underflow interrupt)
Seiko epson Corporation
x - 2
x - 3
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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