Differential Registers And Interrupt Function - Epson S1C6S3N2 Technical Manual

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Differential registers
and interrupt func-
tion
Fig. 4.4.2
Input interrupt circuit
configuration
(K00–K03, K10)
I-32
All five bits of the input ports (K00–K03, K10) provide the
interrupt function. The conditions for issuing an interrupt
can be set by the software. Further, whether to mask the
interrupt function can be selected individually for all five
bits by the software.
Figure 4.4.2 shows the configuration of K00–K03 and K10.
K
Address
Differential
register (DFK)
Address
Interrupt mask
register (EIK)
Address
The input interrupt timing for K00–K03 and K10 depends
on the value set for the differential registers (DFK00–DFK03
and DFK10). Interrupt can be selected to occur at the rising
or falling edge of the input.
The interrupt mask registers (EIK00–EIK03, EIK10) enables
the interrupt mask to be selected individually for K00–K03
and K10. However, whereas the interrupt function is ena-
bled inside K00–K03, the interrupt occurs when the con-
tents change from matching those of the differential register
to non-matching contents. Interrupt for K10 can be gener-
ated by setting the same conditions individually.
When the interrupt is generated, the interrupt factor flag
(IK0 and IK1) is set to "1".
Figure 4.4.3 shows an example of an interrupt for K00–K03.
One for each terminal series
Noise
rejector
Mask option
(K00–K03, K10)
EPSON
Interrupt factor
flag (IK)
Address
S1C6S3N2 TECHNICAL HARDWARE
Interrupt
request