Mitsubishi Electric Q26UD(E)HCPU User Manual page 594

Number Name Meaning
Axis 1
External I/O
SD1847 external I/O
signals
signal
Axis 1
Movement
movement
SD1848, amount after
amount after
SD1849 near-point
near-point
dog ON
dog ON
Axis 1 Data
Data No. of
No. of
positioning
SD1850 positioning
being
being
executed
executed
592
Explanation
• This register stores the on/off status of external I/O
signals.
• When an OPR method with the OPR retry function (Near-
point dog method, Count 1, Count 2) is performed, a value
indicating the status of the upper limit signal or the lower
limit signal is stored to the external command signal.
b15 b6 b5 b4 b3 b2 b1 b0
to
0 0/1 0/1 0/1 0/1 0/1 0/1
*1 When an OPR method with the OPR retry function is
performed even once, a value indicating the status of
the upper limit signal or the lower limit signal will be
stored until when speed/position switching control is
started.
• This register stores "0" when machine OPR control is
started.
• After machine OPR control is started, this register stores a
travel distance from the point where the near-point dog
signal turns on (The point is set to "0".) to the point where
machine OPR control is completed.
• When an OPR method is set to Stopper 3, this register
always stores "0".
*1 Range: 0 to 2147483647 pulses
• This register stores the data No. of positioning being
executed. (A storage value will be held until the next
control starts.)
• "0" is stored when JOG operation or machine OPR control
is started.
• "1" is stored when high-speed OPR control is started.
• "1" is stored when positioning control is started by the
IPDSTRT1 or IPDSTRT2 instruction.
• If an error occurs at the start of positioning control, the
previous value will be held.
Set by
(When Set)
*1
Lower limit signal
0: OFF
1: ON
Upper limit signal
0: OFF
1: ON
S (Every
Near-point dog signal
END
0: OFF
1: ON
processing)
Drive unit ready signal
0: OFF
1: ON
External command signal
0: OFF
1: ON
Zero signal
0: OFF
1: ON
Fixed to 0.
S (Every
END
*1
processing)
S (Every
END
processing)
Corresponding Corresponding
ACPUD9 CPU
New LCPU
New LCPU
New LCPU