Mitsubishi Electric Q26UD(E)HCPU User Manual page 528

Number Name Meaning
0: Main
base
only
Extension 1 to 7:
stage Number
number of
extensio
n base
SD241
units
0: Main
only
Number of 1 to 3:
extension Number
blocks of
extensio
n blocks
Base type
differentiation
0: QA**B
is
installed
A/Q base
(A
differentiation
mode)
1: Q**B is
installed
(Q
mode)
Base type
differentiation
Installed Q
0: Base
base
not
presence/a
installed
bsence
1: Q**B is
installed
SD242
Base type
differentiation
0:
QA1S**
B,
QA1S6
ADP+A
1S*B,
QA**B,
A/Q base
and
differentiation
QA6AD
P+ A**B
are
installed
/ Base
not
installed
1: Q**B is
installed
526
Explanation
This register stores the maximum number of extension base
units installed.
This register stores the maximum number of connected
extension blocks.
b7 b2 b1 b0
Fixed to 0 to
b4 b2 b1 b0
Fixed to 0
to
b7 b2 b1 b0
Fixed to 0 to
• For the Q00UJCPU, the bits for the third to seventh
extension bases are fixed to "0".
• For the Q00UCPU, Q01UCPU, and Q02UCPU, the bits for
the fifth to seventh extension bases are fixed to "0".
Set by
(When Set)
S (Initial)
Main base unit
1st extension base
Fixed to 0
2nd extension base
when the
to
base is not
installed.
7th extension base
Main base unit
1st extension base
2nd extension base
to
4th extension base
S (Initial)
Main base unit
1st extension base
Fixed to 0
2nd extension base
when the
to base is not
installed.
7th extension base
Corresponding
Corresponding
ACPU
CPU
D9
QCPU
New
*9
LCPU
Qn(H)
QnPH
QnPRH
Q00J/Q00/Q01
New
QnU