Mitsubishi Electric Q26UD(E)HCPU User Manual page 534

Number Name Meaning
Number of
SD340 mounted
modules
SD341 I/O No.
Network
SD342
No.
Group
SD343
No.
Station
SD344
No.
SD345
Ethernet
Empty
SD346
information
SD347 Empty
SD348 Information
to from 2nd
SD354 module
SD355 Information
to from 3rd
SD361 module
SD362 Information
to from 4th
SD368 module
Ethernet Instruction
instruction reception
SD380
reception status of 1st
status module
Instruction
reception
SD381
status of 2nd
module
Ethernet Instruction
instruction reception
SD382
reception status of 3rd
status module
Instruction
reception
SD383
status of 4th
module
532
Explanation
Indicates the number of mounted Ethernet modules.
Indicates I/O No. of mounted Ethernet module.
Indicates network No. of mounted Ethernet module.
Indicates group No. of the mounted Ethernet module.
Indicates station No. of mounted Ethernet module.
Empty (The IP address of the 1st Ethernet module is stored in
the buffer memory.)
Empty (An error code of the 1st Ethernet module is read with
the ERRRD instruction.)
Data configuration is the same as that of the 1st module
(SD341 to SD347).
Data configuration is the same as that of the 1st module
(SD341 to SD347).
Data configuration is the same as that of the 1st module
(SD341 to SD347).
b15 to b8 b7 b6 b5 b4 b3 b2
0
Not used
ON: Received (Channel is being used.)
OFF: Not received (Channel is not used.)
Data configuration is the same as that of the 1st module
(SD380).
Data configuration is the same as that of the 1st module
(SD380).
Data configuration is the same as that of the 1st module
(SD380).
Set by
(When Set)
S (Initial)
b1 b0
Instruction reception
status of channel 1
Instruction reception
status of channel 2
Instruction reception
status of channel 3
Instruction reception
(Instruction
status of channel 4
execution)
Instruction reception
status of channel 5
Instruction reception
status of channel 6
Instruction reception
status of channel 7
Instruction reception
status of channel 8
(Instruction
execution)
Corresponding
Corresponding
ACPU
D9
LCPU
New
QnPRH
LCPU
QnPRH
S
New QnPRH
S
New QnPRH
CPU
QCPU
*10
Qn(H)
QnPH
*2
QnU
*10
Qn(H)
QnPH
*3
QnU