Mitsubishi Electric Q26UD(E)HCPU User Manual page 568

Special Special
ACPU
register register
special
after after
register
conversion modification
D9116 SD1116
D9117 SD1117
D9118 SD1118
D9119 SD1119
D9120 SD1120
D9121 SD1121
D9122 SD1122

D9123 SD1123
D9124 SD1124 SD63
D9125 SD1125 SD64
D9126 SD1126 SD65
D9127 SD1127 SD66
D9128 SD1128 SD67
D9129 SD1129 SD68
D9130 SD1130 SD69
D9131 SD1131 SD70
D9132 SD1132 SD71
*1 The following modules support these areas:
• Universal model QCPU whose serial number (first five digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU
*2 Modules whose serial number (first five digits) is "16112" or later
566
Name Meaning
Bit pattern, in units
I/O module of 16 points,
verification indicating the
error modules with
verification errors
Number of Number of
annunciator annunciator
detections detections
Annunciator
Annunciator
detection
detection number
number
Explanation
• If the status of the I/O module changes from that obtained
at power-on, the module No. (unit: 16 points) is stored in
the following bit pattern. (When I/O module numbers
have been set by the parameter, the parameter-set
numbers are stored.)
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1116 0 0 0 0 0 0 0 0
1
SD1117 0 0 0 0 0 0 0
XY
190
1
SD1123 0 0 0 0 0 0 0
XY
7B0
Indicates an I/O module verify error
For a module whose number of I/O points exceeds 16
points, all bits corresponding to I/O module numbers within
the number of I/O points occupied by the module (in
increments of 16 points) turn on.
Example: When a 64-point module is mounted on the slot 0,
b0 to b3 turn on when an error is detected.
• I/O module verification is conducted on I/O modules on
remote I/O stations. (If normal status is restored, clear is
not performed. Therefore, it is required to perform clear
by user program.)
When any of F0 to F2047 (default device setting) is turned
on by the SET F instruction, a value in SD1124 is
incremented by one (up to a maximum of 16). When the
RST F or LEDR instruction is executed, it is decremented
by one.
When any of F0 to F2047 (default device setting) are turned
on by the SET F instruction, the annunciator numbers (F
numbers) that are turned on are stored in SD1125 to
SD1132 in order.
The F numbers turned off by the RST F instruction is
deleted from this register, and the F numbers stored after
the deleted F numbers are shifted to the previous registers.
When the LEDR instruction is executed, the contents of
SD1125 to SD1132 are shifted upward by 1.
When there are eight annunciator detections, the next one
is not stored in SD1125 to SD1132.
SET SET RST SET SET
SET
F50 F25 F99 F25 F15 F70
SD1009 0 0 50 50 50 50 50 50 50 50 50 50
SD1124 0 0 1 1 2 2 3 3 2 2 3 3
SD1125 0 0 50 50 50 50 50 50 50 50 50 50
SD1126 0 0 0 0 25 25 25 25 99 99 99 99
SD1127 0 0 0 0 0 0 99 99 0 0 15 15
SD1128 0 0 0 0 0 0 0 0 0 0 0 0
SD1129 0 0 0 0 0 0 0 0 0 0 0 0
SD1130 0 0 0 0 0 0 0 0 0 0 0 0
SD1131 0 0 0 0 0 0 0 0 0 0 0 0
SD1132 0 0 0 0 0 0 0 0 0 0 0 0
Corresponding
1
0 0 0 0 0 0 0
XY
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
QnU
QnU
QnU
SET
F65 LEDR
(Number
50 50 50 50 99 99
detected)
(Number of
4 4 5 5 4 4
annunciators
detected)
50 50 50 50 99 99
99 99 99 99 15 15
15 15 15 15 70 70
(Number
70 70 70 70 65 65
detected)
0 0 65 65 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
CPU
Qn(H)
QnPH
*1
LCPU
Qn(H)
QnPH
*1
LCPU
Qn(H)
QnPH
*1
LCPU