Mitsubishi Electric Q26UD(E)HCPU User Manual page 518

Number Name Meaning
Bit pattern
indicating
where
SD52 Battery low
battery
voltage drop
occurred
Number of
AC/DC times for
SD53 DOWN AC/DC
detection DOWN
detection
Number of Number of
SD60 module with module with
blown fuse blown fuse
I/O module
I/O module
verify error
SD61 verify error
module
number
number
Annunciator Annunciator
SD62
number number
Number of Number of
SD63
annunciators annunciators
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
Table of
Annunciator
SD74
detected
detection
annunciator
SD75
number
numbers
SD76
SD77
SD78
SD79
SD80 CHK number CHK number
516
Explanation
• This register has the same bit pattern as that of SD51.
• After an alarm is detected (the alarm bit turns on), the alarm
bit turns off if an error is detected (the error bit turns on).
(Universal model QCPU only, except the QnUDVCPU)
• This register stores "0" (turns off) when the battery voltage
returns to normal.
• A value stored in this register is incremented by 1 whenever
the input voltage falls to or below 85% (AC power)/65% (DC
power) of the rating during operation of the CPU module.
• The counter repeats increment and decrement of the value;
0  32767  -32768  0
This register stores the lowest I/O number of the module with
a blown fuse.
This register stores the lowest I/O number of the module
where the I/O module verify error has occurred.
This register stores the number of the annunciator (F number)
detected first.
This register stores the number of detected annunciators.
When an annunciator (F) is turned on by the OUT F or SET F
instruction, the F numbers are stored from SD64 to SD79 in
chronological order.
The number of an annunciator (F) turned off by the RST F
instruction is deleted from SD64 to SD79, and F numbers
stored later than the register where the deleted F number was
stored are shifted upward.
When the LEDR instruction is executed, the contents of SD64
to SD79 are shifted upward by 1. After 16 annunciators have
been detected, detection of the 17th will not be stored from
SD64 through SD79.
SET SET SET RST SET
F50 F25 F99 F25 F15
SD62 0 50 50 50 50 50
SD63 0 1 2 3 2 3
SD64 0 50 50 50 50 50
SD65 0 0 25 25 99 99
SD66 0 0 0 99 0 15
SD67 0 0 0 0 0 0
SD68 0 0 0 0 0 0
SD69 0 0 0 0 0 0
SD70 0 0 0 0 0 0
SD71 0 0 0 0 0 0
SD72 0 0 0 0 0 0
SD73 0 0 0 0 0 0
SD74 0 0 0 0 0 0
SD75 0 0 0 0 0 0
SD76 0 0 0 0 0 0
SD77 0 0 0 0 0 0
SD78 0 0 0 0 0 0
SD79 0 0 0 0 0 0
Error codes detected by the CHK instruction are stored as
BCD code.
(When Set)
S (Error)
S (Error)
S (Error)
S (Error)
(Instruction
execution)
(Instruction
execution)
SET SET
F70 F65 LEDR
(Number
50 50 99
(Instruction
detected)
4 5 4 execution)
(Number of
annunciators
50 50 99
detected)
99 99 15
15 15 70
70 70 65
0 65 0
0 0 0
0 0 0
0 0 0 (Number
detected)
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
(Instruction
execution)
Corresponding
Set by Corresponding
ACPU
D9
New
D9005
D9000
D9002
S
D9009
S
D9124
D9125
D9126
D9127
D9128
D9129
D9130
D9131
D9132
S
New
S
New
CPU
QCPU
LCPU
QCPU
LCPU
QCPU
*9
LCPU
QCPU
LCPU
QCPU
LCPU
QCPU
LCPU
QCPU
LCPU
Qn(H)
QnPH
QnPRH