Mitsubishi Electric Q26UD(E)HCPU User Manual page 556

Number Name Meaning
Maximum
number of
blocks used
for the
multiple CPU
SD796 high-speed
transmission
dedicated
instruction
(for CPU
No.1)
Maximum
number of
blocks used
for the
multiple CPU
SD797 high-speed
Range of the
transmission
maximum
dedicated
number of
instruction
blocks:
(for CPU
1 to 7 (default: 2)
No.2)
Maximum
If the number out
number of
of the range is
blocks used
set, the number
for the
7 is set.
multiple CPU
SD798 high-speed
transmission
dedicated
instruction
(for CPU
No.3)
Maximum
number of
blocks used
for the
multiple CPU
SD799
high-speed
transmission
dedicated
instruction for
CPU No.4)
*1 Modules whose function version B or later
*2 Modules whose serial number (first five digits) is "04012" or later
*3 Modules whose serial number (first five digits) is "07032" or later
*4 Modules whose serial number (first five digits) is "09012" or later
*5 Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU
*6 The range is 1 to 9 (default: 2) for the Q03UDCPU, Q04UDHCPU, and Q06UDHCPU whose serial number (first five
digits) is "10012" or earlier. If the number out of the range is set, the number 9 is set.
554
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.1). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.1, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM796 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.2). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.2, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM797 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.3). When the multiple
*6
CPU high-speed transmission dedicated instruction is
executed to the CPU No.3, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM798 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.4). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.4, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM799 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Explanation
Set by Corresponding
Corresponding
(When ACPU
Set) D9
U (At 1
scan after New
RUN)
CPU
*5
QnU