Mitsubishi Electric Q26UD(E)HCPU User Manual page 530

Number Name Meaning
SD280
Error
CC-Link
detection
error
status
SD281
SD282 Points
assigned to D
(for internal
SD283
device
extension)
Device
SD284 Points
assignment
assigned to
W (for
internal
SD285
device
extension)
528
Explanation
This register stores error detection status in the following bit
pattern.
Information Information
of 3) of 2)
b15 b12 b11 b8 b7
to to to
Empty
1): When Xn0 of a mounted CC-Link module turns on, the
corresponding bit is set to 1 (on).
2): When either Xn1 or XnF of a mounted CC-Link module
turns off, the corresponding bit is set to 1 (on).
3): When a mounted CC-Link module is not able to
communicate with the CPU module, the corresponding
bit is set to 1 (on).
The above modules are numbered in order of the start I/O
numbers. (However, the one where no start I/O number is set
in parameter is not counted.)
This register stores error detection status in the following bit
pattern.
Information Information
of 3) of 2)
b15 b12 b11 b8 b7
to to to
Empty
1): When Xn0 of a mounted CC-Link module turns on, the
corresponding bit is set to 1 (on).
2): When either Xn1 or XnF of a mounted CC-Link module
turns off, the corresponding bit is set to 1 (on).
3): When a mounted CC-Link module is not able to
communicate with the CPU module, the corresponding
bit is set to 1 (on).
The above modules are numbered in order of the start I/O
numbers. (However, the one where no start I/O number is set
in parameter is not counted.)
• The number of points assigned to D is stored with 32 bits.
(except the number of extended data registers)
• The number of 32k or less points can be assigned to D.
• The number of points assigned to W is stored with 32 bits.
(except the number of extended link registers)
• The number of 32k or less points can be assigned to W.
Set by
(When Set)
Information
of 1)
b4 b3 b0
to
1st
module
2nd
module
3rd
module
4th
module
S (Error)
Information
of 1)
b4 b3 b0
to
5th
module
6th
module
7th
module
8th
module
S (Initial)
Corresponding
Corresponding
ACPU
CPU
D9
Qn(H)
QnPH
QnPRH
New
*4
Qn(H)
*4
QnPH
*5
QnPRH
New QnUDV