Mitsubishi Electric Q26UD(E)HCPU User Manual page 567

Special Special
ACPU
register register
special
after after
register
conversion modification
D9095 SD1095 SD200
D9100 SD1100
D9101 SD1101
D9102 SD1102
D9103 SD1103
D9104 SD1104
D9105 SD1105
D9106 SD1106

D9107 SD1107
D9108 SD1108
D9109 SD1109
D9110 SD1110
D9111 SD1111
D9112 SD1112

D9113 SD1113
D9114 SD1114
Name Meaning
DIP switch DIP switch
information information
Bit pattern in units
of 16 points,
Fuse blown
indicating the
module
modules whose
fuses have blown
Step
Timer setting valve
transfer
and the F number
monitoring
at time out
timer setting
Explanation
This register stores a status of the DIP switch of the CPU
module in the following format.
• 0: OFF
• 1: ON
b15 to b5 b4 b3 b2
D9095 0
• The number of an output module whose fuse has blown
is stored in the following bit pattern (in units of 16 points).
(If the module numbers are set by parameter, the
parameter-set numbers are stored.)
b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1
0 0 0 0 0 0 0
SD1100
(YC0) (Y80)
0 0 0 0 0 0 0 0 0
SD1101
1
0 0 0 0 0 0 0 0
SD1107
Y7
B0
Indicates a fuse blown state.
For a module whose number of output points exceeds 16
points, all bits corresponding to output module numbers
within the number of output points occupied by the module
(in increments of 16 points) turn on.
Example: When a 64-point module is mounted on the slot 0,
b0 to b3 turn on when the fuse has blown.
• Output modules on remote I/O stations are also checked
for blown fuse. (This register must be cleared by a
program because the bit status remains unchanged even
after clearing the error.)
• This register stores a value set for step transition
monitoring timer and the number of an annunciator (F
number) that turns on if the monitoring timer times out.
b15 to b8 b7
F number setting Timer time limit setting
(02 to 255) (1 to 255s (1s units))
• Turning on any of registers SM1108 to SM1114 activates
a monitoring timer. If the transition condition for the step
is not established before the time-out time, the
annunciator (F) turns on.
APPENDICES
Corresponding
CPU
Qn(H)
b1 b0
QnPH
SW1
SW2
SW3
SW4
SW5
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1
Qn(H)
0 0 0 0 0 0
Y7
30
QnPH
*1
QnU
*2
LCPU
to b0
Qn(H)
QnPH
565
A