Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
Procedure
Step 1 Run:
system-view
The system view is displayed.
Step 2 Run:
clock id id source source
The ID of a clock source is set.
By default, there is no ID.
Step 3 (Optional) Run:
clock no-id-out { bits0 | bits1 }
The BITS0 or BITS1 interface is disabled from sending the ID of the clock source.
Step 4 (Optional) Run:
interface interface-type interface-number
The interface view is displayed.
Step 5 (Optional) Run:
clock no-id-out
The interface is disabled from sending the ID of the clock source.
----End
11.7.4 Configuring Attributes of the S1 Byte
Context
A multiframe transmitted between BITS interfaces consists of eight sub-multiframes. Each
frame contains five spare bits, namely, SA4 bit to SA8 bit. You can select any one of the spare
SA bits to transmit the SDH synchronization code (S1 byte). The eight frames jointly carry the
eight bits of the S1 byte.
You can specify the SA bit that is used to transmit the S1 byte.
In special scenarios, you need to manually set the S1 byte that an interface sends to adjust the
SSM quality level.
Do as follows on the S9300 according to the actual situation.
Procedure
Step 1 Run:
system-view
The system view is displayed.
Step 2 Run:
clock recv-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 }
The bit of the SA bits from which the SDH synchronization status code (S1 byte) is received is
specified.
Issue 03 (2011-12-29)
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
11 Ethernet Clock Syntonization Configuration
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