Huawei Quidway S9300 Configuration Manual page 210

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
[SwitchB] clock ql-enable extend
[SwitchB] interface GigabitEthernet 5/0/7
[SwitchB-GigabitEthernet5/0/7] clock right-frame 10
[SwitchB-GigabitEthernet5/0/7] quit
[SwitchB] interface GigabitEthernet 5/0/3
[SwitchB-GigabitEthernet5/0/3] clock right-frame 20
[SwitchB-GigabitEthernet5/0/3] quit
[SwitchB] clock priority 6 source 6 system
[SwitchB] quit
# View information about the clock sources sent from the right side of the frame. You can see
that the clock source of GigabitEthernet 5/0/7 is sent to the clock board, and the clock
syntonization direction is shown by the red arrows in
[SwitchB] display clock right-frame
Interface
---------------------------------------------------------------------
GigabitEthernet5/0/3
GigabitEthernet5/0/7
# View the clock information on Switch B, and you can see that the inner clock, Right Frame
Clock, and system clock provide clock signals normally.
[SwitchB] display clock priority
Reference Clock Source
---------------------------------------------------------------------
0
1
2
3
4
5
6
7
8
9
# Verify that the SSM quality level is used in clock source selection.
[SwitchB] display clock mode
QL-Enable
Freq-Check : No.
Retrieve
Hold Type
Run Mode
Bits0
Bits1
System mode: Auto select clock source 6: Right Frame Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
# Ensure that the system clock selects the clock source sent from the right side of the frame as
the clock source and that the system clock sends clock signal to the LPUs as the output clock
signal.
[SwitchB] display clock selection
Type
---------------------------------------------------------------------
system
bits0
bits1
Step 3 Set the mode of clock source selection on Switch C.
# On Switch C, set the priority of the clock signal that GigabitEthernet 2/0/3 sends from the left
side of the frame to 30, and set priority of the clock signal that GigabitEthernet 2/0/0 sends from
Issue 03 (2011-12-29)
Priority
20
10
System
Inner Clock 254
BITS0 1
BITS1 255
Peer Board BITS0 255
Peer Board BITS1 255
Left Frame Clock 255
Right Frame Clock 255
FSU 255
Peer Board FSU 255
System Clock -
: Yes (Extend Mode).
: Yes.
: Hold 24 hours.
: Trace.(SyncOK, Locked)
: Locked.
: Locked.
Clock Source Selected
6.
9.
9.
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
11 Ethernet Clock Syntonization Configuration
Figure 11-3.
Clock Signal Selected
N
Y
bits0
-
-
-
-
-
255
255
255
255
254
Right Frame Clock
System Clock
System Clock
bits1
-
-
-
-
-
255
255
255
255
254
198