Huawei Quidway S9300 Configuration Manual page 206

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
# Ensure that the system clock selects the clock source sent from the right side of the frame as
the clock source and that the system clock sends clock signal to the LPUs as the output clock
signal.
[SwitchB] display clock selection
Type
---------------------------------------------------------------------
system
bits0
bits1
Step 3 Set the mode of clock source selection on Switch C.
# On Switch C, set the priority of the clock signal that GigabitEthernet 2/0/3 sends from the left
side of the frame to 30, and set priority of the clock signal that GigabitEthernet 2/0/0 sends from
the left side of the frame to 40. Retain the default WTR time. Set the priority of the clock signal
sent from the left side of the frame to 5.
<Quidway> system-view
[Quidway] sysname SwitchC
[SwitchC] clock ql-enable
[SwitchC] interface GigabitEthernet 2/0/3
[SwitchC-GigabitEthernet2/0/3] clock left-frame 30
[SwitchC-GigabitEthernet2/0/3] quit
[SwitchC] interface GigabitEthernet 2/0/0
[SwitchC-GigabitEthernet2/0/0] clock left-frame 40
[SwitchC-GigabitEthernet2/0/0] quit
[SwitchC] clock priority 5 source 5 system
[SwitchC] quit
# View information about the clock sources sent from the left side of the frame. You can see
that the clock source of GigabitEthernet 2/0/3 is sent to the clock board, and the clock
syntonization direction is shown by the red arrows in
[SwitchC] display clock left-frame
Interface
---------------------------------------------------------------------
GigabitEthernet2/0/0
GigabitEthernet2/0/3
# View the clock information on Switch C, and you can see that the inner clock, Left Frame
Clock, and system clock provide clock signals normally.
[SwitchC] display clock source
Reference Clock Source
---------------------------------------------------------------------
0
1
2
3
4
5
6
7
8
9
# Verify that the SSM quality level is used in clock source selection.
[SwitchC] display clock mode
QL-Enable
Issue 03 (2011-12-29)
NOTE
If you want to see the clock source switching result during debugging, set the WTR time to 0.
Inner Clock
BITS0
BITS1
Peer Board BITS0
Peer Board BITS1
Left Frame Clock
Right Frame Clock
FSU
Peer Board FSU
System Clock
: Yes.
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11 Ethernet Clock Syntonization Configuration
Clock Source Selected
6. Right Frame Clock
9. System Clock
9. System Clock
Figure
Priority
40
30
Signal Fail S1 Byte
No --
Yes --
Yes --
Yes --
Yes --
No 02
Yes --
Yes --
Yes --
No --
11-2.
Clock Signal Selected
N
Y
ID SSM
- SEC
- DNU
- DNU
- DNU
- DNU
- PRC
- DNU
- DNU
- DNU
- PRC
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