Huawei Quidway S9300 Configuration Manual page 221

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
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Before configuring encapsulation modes for 1588v2 packets, check the link type for 1588v2
packet transmission:
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Two Delay Measurement Mechanisms Supported by the S9300
The S9300 supports the following link delay measurement mechanisms configured for 1588v2:
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Timestamp Modes Supported by the S9300
When packets are used for clock synchronization, the S9300 supports the following modes of
the timestamp carried in packets:
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BMC Algorithm Supported by the S9300
The S9300 supports the BMC algorithm.
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By default, the S9300 synchronizes the time by obtaining frequency signals through Ethernet
synchronization and clock signals through 1588v2. When you use PTP devices, it is
recommended that frequency signals and clock signals be obtained through 1588v2.
PTP Constraints
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Issue 03 (2011-12-29)
In MAC encapsulation mode, the VLAN ID carried in 1588v2 packets is optional. The
MAC encapsulation is classified into two types:
– Unicast encapsulation
– Multicast encapsulation
In UDP encapsulation mode, the VLAN ID carried in 1588v2 packets is optional. The UDP
encapsulation is classified into two types:
– Unicast encapsulation
– Multicast encapsulation
The Layer 2 link adopts the MAC encapsulation mode for 1588v2 packets.
The Layer 3 link adopts the UDP encapsulation mode for 1588v2 packets.
Delay: Delay request-response mechanism
PDelay: Peer delay mechanism
One-step clock mode: In one-step clock mode, Sync messages in Delay mode and
PDelay_Resp messages in PDelay mode are stamped with the time when they are sent.
Two-step clock mode: In two-step clock mode, Sync messages in Delay mode and
PDelay_Resp messages in PDelay mode only record the time when they are generated, but
carry no timestamps. The timestamps are carried in subsequent messages, that is,
Follow_Up or PDelay_Resp_Follow_Up messages.
Best master clock (BMC)
With the BMC algorithm, 1588v2 devices can dynamically select the best master clock on
the network to ensure clock accuracy of devices.
When the S9300 are installed with two MPUs, both the active MPU and slave MPU need
to be configured with the clock boards. If the system needs to synchronize the time by
receiving the external time signal through the BITS interface, the same BITS interface of
the two MPUs (for example, BITS0 interface) must receive the same external time signal.
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