Huawei Quidway S9300 Configuration Manual page 202

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
# View the clock information on Switch C. You can see that the inner clock, Left Frame Clock,
and system clock provide clock signals normally.
[SwitchC] display clock source
Reference Clock Source
---------------------------------------------------------------------
0
1
2
3
4
5
6
7
8
9
# Verify that the SSM quality level is not used in clock source selection.
[SwitchC] display clock mode
QL-Enable
Freq-Check : No.
Retrieve
Hold Type
Run Mode
Bits0
Bits1
System mode: Auto select clock source 5: Left Frame Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
# Verify that the system clock selects the clock source sent from the left side of the frame as the
clock source and that the system clock sends the clock signal to the LPUs as the output clock
signal.
[SwitchC] display clock selection
Type
---------------------------------------------------------------------
system
bits0
bits1
Step 4 Verify the configuration.
The commands used to verify the configuration result are included in the preceding steps.
----End
Configuration Files
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Issue 03 (2011-12-29)
Inner Clock
BITS0
BITS1
Peer Board BITS0
Peer Board BITS1
Left Frame Clock
Right Frame Clock
FSU
Peer Board FSU
System Clock
: No.
: Yes.
: Hold 24 hours.
: Trace.(SyncOK, Locked)
: Locked.
: Locked.
Configuration file of Switch A
#
sysname SwitchA
#
clock priority 1 source 1 system
#
Configuration file of Switch B
#
sysname SwitchB
#
clock priority 6 source 6 system
#
interface GigabitEthernet5/0/3
clock right-frame 20
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Copyright © Huawei Technologies Co., Ltd.
11 Ethernet Clock Syntonization Configuration
Signal Fail S1 Byte
No --
Yes --
Yes --
Yes --
Yes --
No 0f
Yes --
Yes --
Yes --
No --
Clock Source Selected
5. Left Frame Clock
9. System Clock
9. System Clock
ID SSM
- SEC
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- SEC
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