Huawei Quidway S9300 Configuration Manual page 253

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
<Master> system-view
[Master] clock bits-type hz-2m bits0
[Master] clock priority 1 source 1 system
[Master] clock manual-switch source 1 system
[Master] clock bits-type 1pps-tod in bits1
[Master] ptp clock-source bits1 on
Step 3 Configure attributes for the BITS clock source on Master.
[Master] ptp clock-source bits1 time-source 2
BITS is connected to an external time source, namely, GPS, and its time-source is 2.
Step 4 Enable basic 1588v2 functions on Master and configure the device type as OC.
<Master> system-view
[Master] ptp enable
[Master] ptp device-type oc
[Master] interface gigabitethernet 1/0/0
[Master-GigabitEthernet1/0/0] ptp delay-mechanism pdelay
[Master-GigabitEthernet1/0/0] ptp enable
[Master-GigabitEthernet1/0/0] quit
Step 5 Verify the configuration.
After the preceding configurations, run the display clock source command in any view on
Master. You can view that BITS0 and BITS1 on Master are in Normal state, indicating that
Master has successfully traced the BITS clock source.
<Master> display clock source
Reference Clock Source
---------------------------------------------------------------------
0
1
2
3
4
5
6
7
8
9
Run the display clock mode command in system view on Master. You can view that Master
has stepped into lock mode, which means the frequency of Master has traced the signal from
BITS0 port.
<Master> system-view
[Master] display clock mode
QL-Enable
Freq-Check : No.
Retrieve
Hold Type
Run Mode
Bits0
Bits1
System mode: Manual-switch to clock source 1: BITS0.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : 1pps-tod time from bits1
Issue 03 (2011-12-29)
NOTE
The default WTR time of a clock source is 1 minute. Generally, you do not need to change the default
value.
If you want to see the clock source switching result during debugging, set the WTR time to 0.
NOTE
Inner Clock
BITS0
BITS1
Peer Board BITS0
Peer Board BITS1
Left Frame Clock
Right Frame Clock
FSU
Peer Board FSU
System Clock
: No.
: Yes.
: Hold 24 hours.
: Trace.(SyncOK)
: Locked.
: Locked.
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Copyright © Huawei Technologies Co., Ltd.
Signal Fail S1 Byte
No --
No 0f
Yes --
Yes --
Yes --
Yes --
Yes --
Yes --
Yes --
No --
12 PTP Configuration
ID SSM
- SEC
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
- DNU
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