Establishing The Configuration Task - Huawei Quidway S9300 Configuration Manual

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management

11.7.1 Establishing the Configuration Task

Applicable Environment
To control clock syntonization more effectively, perform the following operations:
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Pre-configuration Tasks
Before configuring the attributes of a clock source, complete the following tasks:
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Data Preparation
To configure the attributes of a clock source, you need the following data.
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Issue 03 (2011-12-29)
Set the transmission mode of clock syntonization and time synchronization of a BITS clock.
Set the ID of a clock source to prevent timing loops generated in the SSM extended mode.
Set the priorities of the clock sources provided by different interfaces to specify the
sequence of the clock signals sent from different interfaces to the main control board. Only
the interface of the highest priority can send the clock signal to the main control board.
Lock a clock source to prevent the clock source from being selected.
Enable the result of frequency offset check to affect clock source selection. The clock
sources with greater frequency offset have lower priority in clock source selection.
Set the delay time for the system to consider a clock source lost and the wait-to-restore
(WTR) time of the clock source to prevent frequent switchover of clock sources caused by
network flapping.
Set the permanent holding mode. In this mode, when all the clock sources are lost, the clock
module enters the holding state and retains the original frequency offset according to the
clock information traced before.
NOTE
The permanent holding mode is not recommended.
Set the non-retrieve mode. In this mode, the system changes the clock source only when
the original clock source fails.
Setting parameters of the link layer protocol and IP addresses for the interfaces to ensure
that the link layer protocol on the interfaces is in Up state
Configuring the routing protocol to make the IP routes between the nodes reachable
Setting the mode of clock source selection, that is, based on the SSM quality level or priority
Data
Clock mode or time mode of a BITS clock
ID of the clock source
Priority of the clock source provided by an interface
Clock source to be locked
Delay time for the system to consider a clock source lost
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11 Ethernet Clock Syntonization Configuration
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