Huawei Quidway S9300 Configuration Manual page 177

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
Clock Sources Supported by the S9300
Table 11-1 Clock sources supported by the S9300
Clock No.
0
1
2
3
4
5
6
7
8
9
10
The clock sources are described as follows:
l
Issue 03 (2011-12-29)
Name
Inner Clock
BITS0
BITS1
Peer Board
BITS0
Peer Board
BITS1
Left Frame Clock
Right Frame
Clock
FSU
Peer Board FSU
System Clock
Peer System
Clock
The system clock, BITS0 clock, and BITS1 clock are external clocks used to synchronize
clock signals. Only external clocks need to select the clock source.
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11 Ethernet Clock Syntonization Configuration
Description
Clock signal generated by the local oscillator of clock
board.
Clock signal sent or received by the BITS0 interface of
the master main control board on local device.
Clock signal sent or received by the BITS1 interface of
the master main control board on local device.
Clock signal sent or received by the BITS0 interface of
the slave main control board on local device.
Clock signal sent or received by the BITS1 interface of
the slave main control board on local device.
Clock signal sent from the left side of the frame by the
LPUs with smaller slot IDs.
l On the S9312, LPUs in slot 1 to slot 6 send clock
signals from the left side of the frame.
l On the S9306 and S9303, LPUs in slot 1 to slot 3 send
clock signals from the left side of the frame.
Clock signal sent from the right side of the frame by the
LPUs with greater slot IDs.
l On the S9312, LPUs in slot 7 to slot 12 send clock
signals from the right side of the frame.
l On the S9306, LPUs in slot 4 to slot 6 send clock
signals from the right side of the frame.
NOTE
All boards of the S9303 send clock signals from the left side of
the frame. Therefore, the S9303 does not have this clock.
Clock source on the Flexible Service Unit (FSU). This
clock source is reserved.
Clock source on the FSU of peer board (MPU). This
clock source is reserved.
System clock.
System clock of the peer board (MPU).
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